Messages in this thread | | | Subject | Re: [PATCH v7 08/12] arm: dts: s5pv210: Add node for SGX 540 | From | Jonathan Bakker <> | Date | Sun, 26 Apr 2020 07:57:12 -0700 |
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Hi Paul,
On 2020-04-26 5:56 a.m., Paul Cercueil wrote: > > > Le ven. 24 avril 2020 à 22:34, H. Nikolaus Schaller <hns@goldelico.com> a écrit : >> From: Jonathan Bakker <xc-racer2@live.ca> >> >> All s5pv210 devices have a PowerVR SGX 540 (revision 120) attached. >> >> There is no external regulator for it so it can be enabled by default. >> >> Signed-off-by: Jonathan Bakker <xc-racer2@live.ca> >> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> >> --- >> arch/arm/boot/dts/s5pv210.dtsi | 13 +++++++++++++ >> 1 file changed, 13 insertions(+) >> >> diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi >> index 2ad642f51fd9..abbdda205c1b 100644 >> --- a/arch/arm/boot/dts/s5pv210.dtsi >> +++ b/arch/arm/boot/dts/s5pv210.dtsi >> @@ -512,6 +512,19 @@ vic3: interrupt-controller@f2300000 { >> #interrupt-cells = <1>; >> }; >> >> + gpu: gpu@f3000000 { >> + compatible = "samsung,s5pv210-sgx540-120"; >> + reg = <0xf3000000 0x10000>; >> + interrupt-parent = <&vic2>; >> + interrupts = <10>; >> + clock-names = "core"; >> + clocks = <&clocks CLK_G3D>; >> + >> + assigned-clocks = <&clocks MOUT_G3D>, <&clocks DOUT_G3D>; >> + assigned-clock-rates = <0>, <66700000>; >> + assigned-clock-parents = <&clocks MOUT_MPLL>; > > What are these clocks for, and why are they reparented / reclocked? > > Shouldn't they be passed to 'clocks' as well? > > -Paul >
The G3D clock system can have multiple parents, and for stable operation it's recommended to use the MPLL clock as the parent (which in turn is actually a mux as well). MOUT_G3D is simply the mux for CLK_G3D (SGX core clock), DOUT_G3D is the divider. DOUT_G3D could equally be CLK_G3D (and probably should be, for readability) as CLK_G3D is simply the gate and DOUT_G3D is the divider for it.
The SGX clock layout on S5PV210 looks something like this:
MOUT_MPLL -----------> MOUT_G3D ---> DOUT_G3D ---> CLK_G3D (selectable parent clock) (mux) ---> (divider) ---> (gate)
This is fairly common for older Samsung SoCs, eg having a look at arch/arm/boot/dts/exynos4210-universal_c210.dts you can see that the FIMC clocks are parented to MPLL and have a rate set.
>> + }; >> + >> fimd: fimd@f8000000 { >> compatible = "samsung,s5pv210-fimd"; >> interrupt-parent = <&vic2>; >> -- >> 2.25.1 >> > >
Thanks, Jonathan
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