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    Subject[PATCH v2 53/91] drm/vc4: crtc: Add FIFO depth to vc4_crtc_data
    Date
    Not all pixelvalve FIFOs in vc5 have the same depth, so we need to add that
    to our vc4_crtc_data structure to be able to compute the fill level
    properly later on.

    Signed-off-by: Maxime Ripard <maxime@cerno.tech>
    ---
    drivers/gpu/drm/vc4/vc4_crtc.c | 19 ++++++++++++++++---
    drivers/gpu/drm/vc4/vc4_drv.h | 3 +++
    2 files changed, 19 insertions(+), 3 deletions(-)

    diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
    index ea55d4ca2766..e9d71153c6c6 100644
    --- a/drivers/gpu/drm/vc4/vc4_crtc.c
    +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
    @@ -251,10 +251,20 @@ vc4_crtc_update_gamma_lut(struct drm_crtc *crtc)
    vc4_crtc_lut_load(crtc);
    }

    -static u32 vc4_get_fifo_full_level(u32 format)
    +static u32 vc4_get_fifo_full_level(struct vc4_crtc *vc4_crtc, u32 format)
    {
    - static const u32 fifo_len_bytes = 64;
    + u32 fifo_len_bytes = vc4_crtc->data->fifo_depth;

    + /*
    + * Pixels are pulled from the HVS if the number of bytes is
    + * lower than the FIFO full level.
    + *
    + * The latency of the pixel fetch mechanism is 6 pixels, so we
    + * need to convert those 6 pixels in bytes, depending on the
    + * format, and then subtract that from the length of the FIFO
    + * to make sure we never end up in a situation where the FIFO
    + * is full.
    + */
    switch (format) {
    case PV_CONTROL_FORMAT_DSIV_16:
    case PV_CONTROL_FORMAT_DSIC_16:
    @@ -369,7 +379,7 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc)

    CRTC_WRITE(PV_CONTROL,
    VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
    - VC4_SET_FIELD(vc4_get_fifo_full_level(format),
    + VC4_SET_FIELD(vc4_get_fifo_full_level(vc4_crtc, format),
    PV_CONTROL_FIFO_LEVEL) |
    VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
    PV_CONTROL_CLR_AT_START |
    @@ -1068,6 +1078,7 @@ static const struct vc4_crtc_data bcm2835_pv0_data = {
    .hvs_available_channels = BIT(0),
    .hvs_output = 0,
    .debugfs_name = "crtc0_regs",
    + .fifo_depth = 64,
    .pixels_per_clock = 1,
    .encoder_types = {
    [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
    @@ -1079,6 +1090,7 @@ static const struct vc4_crtc_data bcm2835_pv1_data = {
    .hvs_available_channels = BIT(2),
    .hvs_output = 2,
    .debugfs_name = "crtc1_regs",
    + .fifo_depth = 64,
    .pixels_per_clock = 1,
    .encoder_types = {
    [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
    @@ -1090,6 +1102,7 @@ static const struct vc4_crtc_data bcm2835_pv2_data = {
    .hvs_available_channels = BIT(1),
    .hvs_output = 1,
    .debugfs_name = "crtc2_regs",
    + .fifo_depth = 64,
    .pixels_per_clock = 1,
    .encoder_types = {
    [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI,
    diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
    index 6468c6df20b6..1ac27f8ec725 100644
    --- a/drivers/gpu/drm/vc4/vc4_drv.h
    +++ b/drivers/gpu/drm/vc4/vc4_drv.h
    @@ -450,6 +450,9 @@ to_vc4_encoder(struct drm_encoder *encoder)
    }

    struct vc4_crtc_data {
    + /* Depth of the PixelValve FIFO in bytes */
    + unsigned int fifo_depth;
    +
    /* Which channels of the HVS can the output source from */
    unsigned int hvs_available_channels;

    --
    git-series 0.9.1
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