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Subject[RFC Patch v1 3/4] irqchip/gic-v3: Enable arch specific IPI as pseudo NMI
Date
Add support to mark arch specific IPI as pseudo NMI. Currently its used
to allows arm64 specific IPI_CALL_NMI_FUNC to be marked as pseudo NMI.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
---
arch/arm64/kernel/smp.c | 5 +++++
drivers/irqchip/irq-gic-v3.c | 14 ++++++++++++++
2 files changed, 19 insertions(+)

diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
index 42fe7bb..27c8ee1 100644
--- a/arch/arm64/kernel/smp.c
+++ b/arch/arm64/kernel/smp.c
@@ -802,6 +802,11 @@ static const char *ipi_types[NR_IPI] __tracepoint_string = {
S(IPI_CALL_NMI_FUNC, "NMI function call interrupts"),
};

+int arch_get_ipinr_nmi(void)
+{
+ return IPI_CALL_NMI_FUNC;
+}
+
static void smp_cross_call(const struct cpumask *target, unsigned int ipinr)
{
trace_ipi_raise(target, ipi_types[ipinr]);
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index be361bf..a3d2cf3 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -1048,6 +1048,11 @@ static int gic_dist_supports_lpis(void)
!gicv3_nolpi);
}

+int __weak arch_get_ipinr_nmi(void)
+{
+ return -1;
+}
+
static void gic_cpu_init(void)
{
void __iomem *rbase;
@@ -1072,6 +1077,15 @@ static void gic_cpu_init(void)

gic_cpu_config(rbase, gic_data.ppi_nr + 16, gic_redist_wait_for_rwp);

+ if (gic_supports_nmi()) {
+ int ipinr;
+
+ ipinr = arch_get_ipinr_nmi();
+ if (ipinr >= 0 && ipinr < 16)
+ writeb_relaxed(GICD_INT_NMI_PRI,
+ rbase + GICD_IPRIORITYR + ipinr);
+ }
+
/* initialise system registers */
gic_cpu_sys_reg_init();
}
--
2.7.4
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