Messages in this thread | | | Subject | Re: [PATCH] clk: qcom: msm8916: Fix the address location of pll->config_reg | From | Stephen Boyd <> | Date | Tue, 21 Apr 2020 19:46:07 -0700 |
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Quoting Bryan O'Donoghue (2020-03-29 05:41:16) > During the process of debugging a processor derived from the msm8916 which > we found the new processor was not starting one of its PLLs. > > After tracing the addresses and writes that downstream was doing and > comparing to upstream it became obvious that we were writing to a different > register location than downstream when trying to configure the PLL. > > This error is also present in upstream msm8916. > > As an example clk-pll.c::clk_pll_recalc_rate wants to write to > pll->config_reg updating the bit-field POST_DIV_RATIO. That bit-field is > defined in PLL_USER_CTL not in PLL_CONFIG_CTL. Taking the BIMC PLL as an > example > > lm80-p0436-13_c_qc_snapdragon_410_processor_hrd.pdf > > 0x01823010 GCC_BIMC_PLL_USER_CTL > 0x01823014 GCC_BIMC_PLL_CONFIG_CTL > > This pattern is repeated for gpll0, gpll1, gpll2 and bimc_pll. > > This error is likely not apparent since the bootloader will already have > initialized these PLLs. > > This patch corrects the location of config_reg from PLL_CONFIG_CTL to > PLL_USER_CTL for all relevant PLLs on msm8916. > > Fixes commit 3966fab8b6ab ("clk: qcom: Add MSM8916 Global Clock Controller support") > > Cc: Georgi Djakov <georgi.djakov@linaro.org> > Cc: Andy Gross <agross@kernel.org> > Cc: Bjorn Andersson <bjorn.andersson@linaro.org> > Cc: Michael Turquette <mturquette@baylibre.com> > Cc: Stephen Boyd <sboyd@kernel.org> > Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> > ---
Applied to clk-next
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