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    Subject[PATCH AUTOSEL 5.5 087/106] drm/vc4: Fix HDMI mode validation
    Date
    From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>

    [ Upstream commit b1e7396a1d0e6af6806337fdaaa44098d6b3343c ]

    Current mode validation impedes setting up some video modes which should
    be supported otherwise. Namely 1920x1200@60Hz.

    Fix this by lowering the minimum HDMI state machine clock to pixel clock
    ratio allowed.

    Fixes: 32e823c63e90 ("drm/vc4: Reject HDMI modes with too high of clocks.")
    Reported-by: Stefan Wahren <stefan.wahren@i2se.com>
    Suggested-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
    Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
    Signed-off-by: Maxime Ripard <maxime@cerno.tech>
    Link: https://patchwork.freedesktop.org/patch/msgid/20200326122001.22215-1-nsaenzjulienne@suse.de
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/gpu/drm/vc4/vc4_hdmi.c | 20 ++++++++++++++++----
    1 file changed, 16 insertions(+), 4 deletions(-)

    diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
    index 1c62c6c9244b7..568953898ce6b 100644
    --- a/drivers/gpu/drm/vc4/vc4_hdmi.c
    +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
    @@ -678,11 +678,23 @@ static enum drm_mode_status
    vc4_hdmi_encoder_mode_valid(struct drm_encoder *crtc,
    const struct drm_display_mode *mode)
    {
    - /* HSM clock must be 108% of the pixel clock. Additionally,
    - * the AXI clock needs to be at least 25% of pixel clock, but
    - * HSM ends up being the limiting factor.
    + /*
    + * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
    + * be faster than pixel clock, infinitesimally faster, tested in
    + * simulation. Otherwise, exact value is unimportant for HDMI
    + * operation." This conflicts with bcm2835's vc4 documentation, which
    + * states HSM's clock has to be at least 108% of the pixel clock.
    + *
    + * Real life tests reveal that vc4's firmware statement holds up, and
    + * users are able to use pixel clocks closer to HSM's, namely for
    + * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
    + * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
    + * 162MHz.
    + *
    + * Additionally, the AXI clock needs to be at least 25% of
    + * pixel clock, but HSM ends up being the limiting factor.
    */
    - if (mode->clock > HSM_CLOCK_FREQ / (1000 * 108 / 100))
    + if (mode->clock > HSM_CLOCK_FREQ / (1000 * 101 / 100))
    return MODE_CLOCK_HIGH;

    return MODE_OK;
    --
    2.20.1
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