lkml.org 
[lkml]   [2020]   [Apr]   [15]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
From
SubjectRE: [PATCH v3 1/2] dt-bindings: edac: Add cadence ddr mc support
Date


> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: Wednesday, April 15, 2020 5:20 AM
> To: Dhananjay Vilasrao Kangude <dkangude@cadence.com>
> Cc: linux-edac@vger.kernel.org; bp@alien8.de; mchehab@kernel.org;
> tony.luck@intel.com; james.morse@arm.com; linux-kernel@vger.kernel.org;
> Milind Parab <mparab@cadence.com>; devicetree@vger.kernel.org
> Subject: Re: [PATCH v3 1/2] dt-bindings: edac: Add cadence ddr mc support
>
> EXTERNAL MAIL
>
>
> On Mon, Apr 06, 2020 at 03:13:40PM +0200, Dhananjay Kangude wrote:
> > Add documentation for cadence ddr memory controller EDAC DTS bindings
> >
> > Signed-off-by: Dhananjay Kangude <dkangude@cadence.com>
> > ---
> > .../devicetree/bindings/edac/cdns,ddr-edac.yaml | 47
> ++++++++++++++++++++
> > 1 files changed, 47 insertions(+), 0 deletions(-) create mode 100644
> > Documentation/devicetree/bindings/edac/cdns,ddr-edac.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/edac/cdns,ddr-edac.yaml
> > b/Documentation/devicetree/bindings/edac/cdns,ddr-edac.yaml
> > new file mode 100644
> > index 0000000..30ea757
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/edac/cdns,ddr-edac.yaml
> > @@ -0,0 +1,47 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> > +https://urldefense.com/v3/__http://devicetree.org/schemas/edac/cdns,d
> > +dr-
> edac.yaml*__;Iw!!EHscmS1ygiU1lA!T49K56JzhGnA7nxu4mq55aDfl80QsXPj-l
> > +Egtf_PILMzq2Np6NqhLRXeTNuBLx0$
> > +$schema:
> > +https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.y
> > +aml*__;Iw!!EHscmS1ygiU1lA!T49K56JzhGnA7nxu4mq55aDfl80QsXPj-
> lEgtf_PILM
> > +zq2Np6NqhLRXe69d40qY$
> > +
> > +title: Cadence DDR IP with ECC support (EDAC)
> > +
> > +description:
> > + This binding describes the Cadence DDR/LPDDR IP with ECC feature
> > +enabled
> > + to detect and correct CE/UE errors.
> > +
> > +maintainers:
> > + - Dhananjay Kangdue <dkangude@cadence.com>
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - cdns,ddr4-mc
>
> Surely there's more than 1 version?

[Dhananjay Kangude] No, as of now we have only one version of hardware module.
I will change the property with items instead of enum.
>
> > +
> > + reg:
> > + minItems: 1
> > + maxItems: 2
> > + items:
> > + - description:
> > + Register block of DDR/LPDDR apb registers up to mapped area.
> > + Mapped area contains the register set for memory controller,
> > + phy and PI module register set doesn't part of this mapping.
>
> doesn't part of this mapping?
>
[Dhananjay Kangude] In case of combo IP, controller and phy module are together.
But ecc doesn't have any dependencies on phy module so we can exclude phy module .
> Need a description for the 2nd region.

[Dhananjay Kangude] Removed maxItems property. We don't have another region to access.
fix will release in next version
>
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + edac: edac@fd100000 {
>
> memory-controller@
[Dhananjay Kangude] ] memory-controller might not the appropriate name.
the driver module is only focused on ecc not on actual memory-controller functionality.
>
> > + compatible = "cdns,ddr4-mc-edac";
>
> Doesn't match.
[Dhananjay Kangude] fixed. Changes will be part of next version.
>
> > + reg = <0xfd100000 0x4000>;
> > + interrupts = <0x00 0x01 0x04>;
> > + };
> > +...
> > --
> > 1.7.1
> >

\
 
 \ /
  Last update: 2020-04-15 16:56    [W:0.064 / U:0.124 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site