Messages in this thread | | | Date | Sat, 11 Apr 2020 11:59:19 +0100 | From | Marc Zyngier <> | Subject | Re: [PATCH] irqchip/sifive-plic: Fix maximum priority threshold value |
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On Thu, 2 Apr 2020 18:46:09 -0700 Atish Patra <atish.patra@wdc.com> wrote:
> As per the PLIC specification, maximum priority threshold value is 0x7 > not 0xF. Even though it doesn't cause any error in qemu/hifive unleashed, > there may be some implementation which checks the upper bound resulting in > an illegal access. > > Fixes: ccbe80bad571 (irqchip/sifive-plic: Enable/Disable external > interrupts upon cpu online/offline)
Small nit: please write the "Fixes:" tag as documented in process/submitting-patches.rst:
Fixes: ccbe80bad571 ("irqchip/sifive-plic: Enable/Disable external interrupts upon cpu online/offline")
(with quotes, and on a single line), as it otherwise breaks with the lore-scrapping tooling which a bunch of us are now using.
> Signed-off-by: Atish Patra <atish.patra@wdc.com> > --- > drivers/irqchip/irq-sifive-plic.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c > index c34fb3ae0ff8..d0a71febdadc 100644 > --- a/drivers/irqchip/irq-sifive-plic.c > +++ b/drivers/irqchip/irq-sifive-plic.c > @@ -56,7 +56,7 @@ > #define CONTEXT_THRESHOLD 0x00 > #define CONTEXT_CLAIM 0x04 > > -#define PLIC_DISABLE_THRESHOLD 0xf > +#define PLIC_DISABLE_THRESHOLD 0x7 > #define PLIC_ENABLE_THRESHOLD 0 > > struct plic_priv {
Queued for post -rc1.
Thanks,
M. -- Jazz is not dead. It just smells funny...
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