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SubjectRe: [PATCH 2/6] arm64/cpufeature: Add DIT and CSV2 feature bits in ID_PFR0 register
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On 03/20/2020 11:37 PM, Suzuki K Poulose wrote:
> Cc: Mark Rutland

Sure, will add this to all the patches here. Also add 'Suggested-by'
tags on all the changes proposed by Mark. Should have already added
that in this version as well, my bad.

>
> On 01/28/2020 12:39 PM, Anshuman Khandual wrote:
>> Enable DIT and CSV2 feature bits in ID_PFR0 register as per ARM DDI 0487E.a
>> specification. Except RAS and AMU, all other feature bits are now enabled.
>>
>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>> Cc: Will Deacon <will@kernel.org>
>> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
>> Cc: linux-kernel@vger.kernel.org
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>
> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>
>> ---
>>   arch/arm64/include/asm/sysreg.h | 3 +++
>>   arch/arm64/kernel/cpufeature.c  | 2 ++
>>   2 files changed, 5 insertions(+)
>>
>> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
>> index 054aab7ebf1b..469d61c8fabf 100644
>> --- a/arch/arm64/include/asm/sysreg.h
>> +++ b/arch/arm64/include/asm/sysreg.h
>> @@ -718,6 +718,9 @@
>>   #define ID_ISAR6_DP_SHIFT        4
>>   #define ID_ISAR6_JSCVT_SHIFT        0
>>   +#define ID_PFR0_DIT_SHIFT        24
>> +#define ID_PFR0_CSV2_SHIFT        16
>> +
>>   #define ID_PFR2_SSBS_SHIFT        4
>>   #define ID_PFR2_CSV3_SHIFT        0
>>   diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
>> index c1e837fc8f97..9e4dab15c608 100644
>> --- a/arch/arm64/kernel/cpufeature.c
>> +++ b/arch/arm64/kernel/cpufeature.c
>> @@ -341,6 +341,8 @@ static const struct arm64_ftr_bits ftr_id_isar6[] = {
>>   };
>>     static const struct arm64_ftr_bits ftr_id_pfr0[] = {
>> +    ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_DIT_SHIFT, 4, 0),
>> +    ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_CSV2_SHIFT, 4, 0),
>>       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),        /* State3 */
>>       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),        /* State2 */
>>       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),        /* State1 */
>>
>
>

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