Messages in this thread Patch in this message | | | From | Thierry Reding <> | Subject | [PATCH v2 4/7] arm64: tegra: Add native timer support on Tegra186 | Date | Wed, 1 Apr 2020 00:19:11 +0200 |
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From: Thierry Reding <treding@nvidia.com>
The native timers IP block found on NVIDIA Tegra SoCs implements a watchdog timer that can be used to recover from system hangs. Add the device tree node on Tegra186.
Signed-off-by: Thierry Reding <treding@nvidia.com> --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 58100fb9cd8b..4dfa70e93693 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -167,6 +167,22 @@ emc: external-memory-controller@2c60000 { }; }; + timer@3010000 { + compatible = "nvidia,tegra186-timer"; + reg = <0x0 0x03010000 0x0 0x000e0000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + uarta: serial@3100000 { compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; reg = <0x0 0x03100000 0x0 0x40>; -- 2.24.1
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