Messages in this thread | | | Subject | Re: [PATCH] perf/x86/intel: Add more available bits for OFFCORE_RESPONSE of Intel Tremont | From | "Liang, Kan" <> | Date | Mon, 30 Mar 2020 10:53:59 -0400 |
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Hi Peter,
Could you please take a look and apply the patch?
Thanks, Kan
On 3/8/2020 8:55 AM, kan.liang@linux.intel.com wrote: > From: Kan Liang <kan.liang@linux.intel.com> > > The mask in the extra_regs for Intel Tremont need to be extended to > allow more defined bits. > > "Outstanding Requests" (bit 63) is only available on MSR_OFFCORE_RSP0; > > Fixes: 6daeb8737f8a ("perf/x86/intel: Add Tremont core PMU support") > Reported-by: Stephane Eranian <eranian@google.com> > Signed-off-by: Kan Liang <kan.liang@linux.intel.com> > Cc: stable@vger.kernel.org > --- > arch/x86/events/intel/core.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c > index 3be51aa06e67..ba08ad1f560b 100644 > --- a/arch/x86/events/intel/core.c > +++ b/arch/x86/events/intel/core.c > @@ -1892,8 +1892,8 @@ static __initconst const u64 tnt_hw_cache_extra_regs > > static struct extra_reg intel_tnt_extra_regs[] __read_mostly = { > /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ > - INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffffff9fffull, RSP_0), > - INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xffffff9fffull, RSP_1), > + INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff0ffffff9fffull, RSP_0), > + INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff0ffffff9fffull, RSP_1), > EVENT_EXTRA_END > }; > >
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