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    Subject[PATCH 5.5 099/176] amdgpu/gmc_v9: save/restore sdpif regs during S3
    Date
    From: Shirish S <shirish.s@amd.com>

    commit a3ed353cf8015ba84a0407a5dc3ffee038166ab0 upstream.

    fixes S3 issue with IOMMU + S/G enabled @ 64M VRAM.

    Suggested-by: Alex Deucher <alexander.deucher@amd.com>
    Signed-off-by: Shirish S <shirish.s@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
    Cc: stable@vger.kernel.org
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 1
    drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 37 ++++++++++++-
    drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h | 2
    3 files changed, 39 insertions(+), 1 deletion(-)

    --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
    +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
    @@ -192,6 +192,7 @@ struct amdgpu_gmc {
    uint32_t srbm_soft_reset;
    bool prt_warning;
    uint64_t stolen_size;
    + uint32_t sdpif_register;
    /* apertures */
    u64 shared_aperture_start;
    u64 shared_aperture_end;
    --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
    +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
    @@ -1204,6 +1204,19 @@ static void gmc_v9_0_init_golden_registe
    }

    /**
    + * gmc_v9_0_restore_registers - restores regs
    + *
    + * @adev: amdgpu_device pointer
    + *
    + * This restores register values, saved at suspend.
    + */
    +static void gmc_v9_0_restore_registers(struct amdgpu_device *adev)
    +{
    + if (adev->asic_type == CHIP_RAVEN)
    + WREG32(mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register);
    +}
    +
    +/**
    * gmc_v9_0_gart_enable - gart enable
    *
    * @adev: amdgpu_device pointer
    @@ -1308,6 +1321,20 @@ static int gmc_v9_0_hw_init(void *handle
    }

    /**
    + * gmc_v9_0_save_registers - saves regs
    + *
    + * @adev: amdgpu_device pointer
    + *
    + * This saves potential register values that should be
    + * restored upon resume
    + */
    +static void gmc_v9_0_save_registers(struct amdgpu_device *adev)
    +{
    + if (adev->asic_type == CHIP_RAVEN)
    + adev->gmc.sdpif_register = RREG32(mmDCHUBBUB_SDPIF_MMIO_CNTRL_0);
    +}
    +
    +/**
    * gmc_v9_0_gart_disable - gart disable
    *
    * @adev: amdgpu_device pointer
    @@ -1343,9 +1370,16 @@ static int gmc_v9_0_hw_fini(void *handle

    static int gmc_v9_0_suspend(void *handle)
    {
    + int r;
    struct amdgpu_device *adev = (struct amdgpu_device *)handle;

    - return gmc_v9_0_hw_fini(adev);
    + r = gmc_v9_0_hw_fini(adev);
    + if (r)
    + return r;
    +
    + gmc_v9_0_save_registers(adev);
    +
    + return 0;
    }

    static int gmc_v9_0_resume(void *handle)
    @@ -1353,6 +1387,7 @@ static int gmc_v9_0_resume(void *handle)
    int r;
    struct amdgpu_device *adev = (struct amdgpu_device *)handle;

    + gmc_v9_0_restore_registers(adev);
    r = gmc_v9_0_hw_init(adev);
    if (r)
    return r;
    --- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h
    +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h
    @@ -7376,6 +7376,8 @@
    #define mmCRTC4_CRTC_DRR_CONTROL 0x0f3e
    #define mmCRTC4_CRTC_DRR_CONTROL_BASE_IDX 2

    +#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x395d
    +#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2

    // addressBlock: dce_dc_fmt4_dispdec
    // base address: 0x2000

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