Messages in this thread | | | Subject | Re: [PATCH] x86: perf: insn: Tweak opcode map for Intel CET instructions | From | Adrian Hunter <> | Date | Tue, 3 Mar 2020 09:17:09 +0200 |
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On 3/03/20 6:50 am, Mingbo Zhang wrote: > Intel CET instructions are not described in the Intel SDM. When trying to > get the instruction length, the following instructions get wrong (missing > ModR/M byte). > > RDSSPD r32 > RSDDPQ r64 > ENDBR32 > ENDBR64 > WRSSD r/m32, r32 > WRSSQ r/m64, r64 > > RDSSPD/Q and ENDBR32/64 use the same opcode (f3 0f 1e) slot, which is > described in SDM as Reserved-NOP with no encoding characters, and got an > empty slot in the opcode map. WRSSD/Q (0f 38 f6) also got an empty slot.
We have patches for that:
https://lore.kernel.org/lkml/20200204171425.28073-1-yu-cheng.yu@intel.com/
But they have not yet been applied. Arnaldo, could you take them?
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