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SubjectRe: [PATCH] x86: perf: insn: Tweak opcode map for Intel CET instructions
Em Thu, Mar 26, 2020 at 07:09:45AM +0200, Adrian Hunter escreveu:
> On 26/03/20 3:31 am, Masami Hiramatsu wrote:
> > Hi,
> >
> > On Mon, 2 Mar 2020 23:50:30 -0500
> > Mingbo Zhang <whensungoes@gmail.com> wrote:
> >
> >> Intel CET instructions are not described in the Intel SDM. When trying to
> >> get the instruction length, the following instructions get wrong (missing
> >> ModR/M byte).
> >>
> >> RDSSPD r32
> >> RSDDPQ r64
> >> ENDBR32
> >> ENDBR64
> >> WRSSD r/m32, r32
> >> WRSSQ r/m64, r64
> >>
> >> RDSSPD/Q and ENDBR32/64 use the same opcode (f3 0f 1e) slot, which is
> >> described in SDM as Reserved-NOP with no encoding characters, and got an
> >> empty slot in the opcode map. WRSSD/Q (0f 38 f6) also got an empty slot.
> >>
> >
> > This looks good to me. BTW, wouldn't we need to add decode test cases to perf?
> >
> > Acked-by: Masami Hiramatsu <mhiramat@kernel.org>
> >
> > Thank you,
> >
>
> We have correct patches that you ack'ed for CET here:
>
> https://lore.kernel.org/lkml/20200204171425.28073-1-yu-cheng.yu@intel.com/
>
> But they have not yet been applied.
>
> Sorry for the confusion.

I'll collect them, thanks for pointing this out.

- Arnaldo

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