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SubjectRe: Two questions about cache coherency on arm platforms
On Mon, Mar 23, 2020 at 04:15:40PM +0000, Changbin Du wrote:
> Hi Mark,
> Thanks for your answer. I still don't understand the first question.
>
> On Mon, Mar 23, 2020 at 01:17:20PM +0000, Mark Rutland wrote:
> > On Mon, Mar 23, 2020 at 08:35:26PM +0800, Changbin Du wrote:
> > > Hi, All,
> > > I am not very familiar with ARM processors. I have two questions about
> > > cache coherency. Could anyone help me?
> > >
> > > 1. How is cache coherency maintenanced on ARMv8 big.LITTLE system?
> > > As far as I know, big cores and little cores are in seperate clusters on
> > > big.LITTLE system.
> >
> > This is often true, but not always the case. For example, with DSU big
> > and little cores can be placed within the same cluster.
>
> Yes, it is ture for DynamIQ that bl cores can be placed within the same cluster.
> But I don't understand how linux support big.LITTLE before DynamIQ.

Multiple clusters can be in the same Inner Shareable domain, and Linux
relies on this being the case for systems it supports. It's possible to
build a system where clusters are in distinct Inner Shareable domains,
but Linux does not support using all cores on such a system.

Even with CCI, CCN, CMN, etc, Linux requires that all cores (which it is
told about) are in the same Inner Shareable domain. That is what is
commonly built.

> I read below description in ARM Cortex-A Series Programmer’s Guide for
> ARMv8-A.
> | big.LITTLE software models require transparent and efficient transfer of data between big and LITTLE clusters.
> | Coherency between clusters is provided by a cache-coherent interconnect such as the ARM CoreLink CCI-400 described in Chapter 14.
>
> So I think big cores and little cores are in different clusters in this
> case. Then we are not within the same Inner Shareable domain?

Linux requires that those clusters are in the same Inner Shareable
domain, and that's what people (mostly) build today.

Thanks,
Mark.

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