Messages in this thread | | | From | "Park, Kyung Min" <> | Subject | RE: [PATCH v2 2/2] x86/delay: Introduce TPAUSE delay | Date | Mon, 23 Mar 2020 05:18:36 +0000 |
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Hi Joe,
> -----Original Message----- > From: Joe Perches <joe@perches.com> > Sent: Friday, March 20, 2020 3:07 AM > To: Park, Kyung Min <kyung.min.park@intel.com>; x86@kernel.org; linux- > kernel@vger.kernel.org > Cc: tglx@linutronix.de; mingo@redhat.com; hpa@zytor.com; > gregkh@linuxfoundation.org; ak@linux.intel.com; Luck, Tony > <tony.luck@intel.com>; Raj, Ashok <ashok.raj@intel.com>; Shankar, Ravi V > <ravi.v.shankar@intel.com>; Yu, Fenghua <fenghua.yu@intel.com> > Subject: Re: [PATCH v2 2/2] x86/delay: Introduce TPAUSE delay > > On Thu, 2020-03-19 at 21:13 -0700, Kyung Min Park wrote: > > TPAUSE instructs the processor to enter an implementation-dependent > > optimized state. The instruction execution wakes up when the > > time-stamp counter reaches or exceeds the implicit EDX:EAX 64-bit input value. > > The instruction execution also wakes up due to the expiration of the > > operating system time-limit or by an external interrupt or exceptions > > such as a debug exception or a machine check exception. > [] > > diff --git a/arch/x86/lib/delay.c b/arch/x86/lib/delay.c > [] > > @@ -97,6 +97,27 @@ static void delay_tsc(u64 cycles) } > > > > /* > > + * On Intel the TPAUSE instruction waits until any of: > > + * 1) the TSC counter exceeds the value provided in EAX:EDX > > + * 2) global timeout in IA32_UMWAIT_CONTROL is exceeded > > + * 3) an external interrupt occurs > > + */ > > +static void delay_halt_tpause(u64 start, u64 cycles) { > > + u64 until = start + cycles; > > + unsigned int eax, edx; > > + > > + eax = (unsigned int)(until & 0xffffffff); > > + edx = (unsigned int)(until >> 32); > > trivia: > > perhaps lower_32_bits and upper_32_bits
Thank you for your comment. I'll update in the next patch.
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