[lkml]   [2020]   [Mar]   [23]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
Messages in this thread
SubjectRe: [RFC PATCH V3 00/11] riscv: Add vector ISA support
Hi Greentime,

On Mon, Mar 23, 2020 at 12:00 PM Greentime Hu <> wrote:
> <> 於 2020年3月8日 週日 下午5:50寫道:
> >
> > From: Guo Ren <>
> >
> > The implementation follow the RISC-V "V" Vector Extension draft v0.8 with
> > 128bit-vlen and it's based on linux-5.6-rc3 and tested with qemu [1].
> >
> > The patch implement basic context switch, sigcontext save/restore and
> > ptrace interface with a new regset NT_RISCV_VECTOR. Only fixed 128bit-vlen
> > is implemented. We need to discuss about vlen-size for libc sigcontext and
> > ptrace (the maximum size of vlen is unlimited in spec).
> >
> > Puzzle:
> > Dave Martin has talked "Growing CPU register state without breaking ABI" [2]
> > before, and riscv also met vlen size problem. Let's discuss the common issue
> > for all architectures and we need a better solution for unlimited vlen.
> >
> > Any help are welcomed :)
> >
> > 1: branch:vector-upstream-v3
> > 2:
> >
> Hi Ren,
> Thanks for the patch. I have some ideas about the vlen and sigcontext.
> Since vlen may not be fixed of each RISC-V cores and it could be super
> big, it means we have to allocate the memory dynamically.
> In kernel space, we may use a pointer in the context data structure.
> Something like
> In user space, we need to let user space know the length of vector
> registers. We may create a special header in sigcontext. Something
> like

As you've mentioned codes above, arm64 use a fixed pre-allocate
sigcontext with a large space:

struct sigcontext {
__u64 fault_address;
/* AArch64 registers */
__u64 regs[31];
__u64 sp;
__u64 pc;
__u64 pstate;
/* 4K reserved for FP/SIMD state and future expansion */
__u8 __reserved[4096] __attribute__((__aligned__(16)));

There are several contexts in the space above: fpsimd, esr, sve, extra
* 0x210 fpsimd_context
* 0x10 esr_context
* 0x8a0 sve_context (vl <= 64) (optional)
* 0x20 extra_context (optional)
* 0x10 terminator (null _aarch64_ctx)
* 0x510 (reserved for future allocation)

0x210 + 0x10 + 0x8a0 + 0x20 + 0x10 + 0x510 = 4096

The max vl is 64 in arm sve, but for riscv want an unlimited size
solution and more extensible/flexible solution, such as dynamic
allocating user-space context with hwinfo. But there is no ref
solution around all arches.

There is a choice puzzle for me:
1) A pre-allocated&limited reserved size of sigcontext, the solution
has been practiced and we just need to determine the size.
2) Dynamically allocated/unlimited size of sigcontext, but may deal
with glibc, libgcc infrastructure on abi view.

Before the next stage of work, we need to choose the direction and
it's also a common puzzle for all architectures with extending
vector/simd like co-processor solutions.

Have a look on Dave's patch, he just follow the arm64 fixed
pre-allocate limited sigcontext infrastructure:
(I don't think it's a proper example for riscv vector design.)

commit d0b8cd3187889476144bd9b13bf36a932c3e7952
Author: Dave Martin <>
Date: Tue Oct 31 15:51:03 2017 +0000

arm64/sve: Signal frame and context structure definition

> For the implementation in makecontext, swapcontext, getcontext,
> setcontext of glibc, we may not need to port because it seems to be
> deprecated?
Agree, we needn't deal with them at beginning.

> For the unwinding implementation of libgcc since it needs to know the
> meaning of data structure is changed. It also need to be port.
Yes, it'll break the abi and such as the elf with -fexception compiled
will be broken.

Best Regards
Guo Ren


 \ /
  Last update: 2020-03-24 04:43    [W:0.134 / U:6.048 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site