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Subject[RFC PATCH 0/7] Introduce sv48 support
Date
This patchset implements sv48 support at runtime. The kernel will try to
boot with 4-level page table and will fallback to 3-level if the HW does not
support it.

The biggest advantage is that we only have one kernel for 64bit, which
is way easier to maintain.

Folding the 4th level into a 3-level page table has almost no cost at
runtime.

At the moment, there is no way to enforce 3-level if the HW supports
4-level page table: early parameters are parsed after the choice must be
made.

It is based on my relocatable patchset v3 that I have not posted yet,
you can try the sv48 support by using the branch
int/alex/riscv_sv48_runtime_v1 here:

https://github.com/AlexGhiti/riscv-linux

Any feedback appreciated,

Thanks,

Alexandre Ghiti (7):
riscv: Get rid of compile time logic with MAX_EARLY_MAPPING_SIZE
riscv: Allow to dynamically define VA_BITS
riscv: Simplify MAXPHYSMEM config
riscv: Implement sv48 support
riscv: Use pgtable_l4_enabled to output mmu type in cpuinfo
dt-bindings: riscv: Remove "riscv,svXX" property from device-tree
riscv: Explicit comment about user virtual address space size

.../devicetree/bindings/riscv/cpus.yaml | 13 --
arch/riscv/Kconfig | 34 ++---
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 4 -
arch/riscv/include/asm/csr.h | 3 +-
arch/riscv/include/asm/fixmap.h | 1 +
arch/riscv/include/asm/page.h | 15 +-
arch/riscv/include/asm/pgalloc.h | 36 +++++
arch/riscv/include/asm/pgtable-64.h | 98 +++++++++++-
arch/riscv/include/asm/pgtable.h | 24 ++-
arch/riscv/include/asm/sparsemem.h | 2 +-
arch/riscv/kernel/cpu.c | 24 +--
arch/riscv/kernel/head.S | 37 ++++-
arch/riscv/mm/context.c | 4 +-
arch/riscv/mm/init.c | 142 +++++++++++++++---
14 files changed, 341 insertions(+), 96 deletions(-)

--
2.20.1

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