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SubjectRe: x2apic_wrmsr_fence vs. Intel manual
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On 02.03.20 17:20, Thomas Gleixner wrote:
> Jan Kiszka <jan.kiszka@siemens.com> writes:
>> as I generated a nice bug around fence vs. x2apic icr writes, I studied
>> the kernel code and the Intel manual in this regard more closely. But
>> there is a discrepancy:
>>
>> arch/x86/include/asm/apic.h:
>>
>> /*
>> * Make previous memory operations globally visible before
>> * sending the IPI through x2apic wrmsr. We need a serializing instruction or
>> * mfence for this.
>> */
>> static inline void x2apic_wrmsr_fence(void)
>> {
>> asm volatile("mfence" : : : "memory");
>> }
>>
>> Intel SDM, 10.12.3 MSR Access in x2APIC Mode:
>>
>> "A WRMSR to an APIC register may complete before all preceding stores
>> are globally visible; software can prevent this by inserting a
>> serializing instruction or the sequence MFENCE;LFENCE before the WRMSR."
>>
>> The former dates back to ce4e240c279a, but that commit does not mention
>> why lfence is not needed. Did the manual read differently back then? Or
>> why are we safe? To my reading of lfence, it also has a certain
>> instruction serializing effect that mfence does not have.
>
> The 2011 SDM says:
>
> A WRMSR to an APIC register may complete before all preceding stores
> are globally visible; software can prevent this by inserting a
> serializing instruction, an SFENCE, or an MFENCE before the WRMSR.
>
> Sigh....
>

OK, that explains it. Curious since when (date and CPU generation) we
unknowingly started to play roulette here.

Jan

--
Siemens AG, Corporate Technology, CT RDA IOT SES-DE
Corporate Competence Center Embedded Linux

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