Messages in this thread | | | From | Logan Gunthorpe <> | Date | Mon, 2 Mar 2020 14:20:07 -0700 | Subject | Re: [PATCH v3 7/7] mm/memremap: Set caching mode for PCI P2PDMA memory to WC |
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On 2020-02-29 3:47 p.m., Dan Williams wrote: > On Fri, Feb 21, 2020 at 10:25 AM Logan Gunthorpe <logang@deltatee.com> wrote: >> >> PCI BAR IO memory should never be mapped as WB, however prior to this >> the PAT bits were set WB and it was typically overridden by MTRR >> registers set by the firmware. >> >> Set PCI P2PDMA memory to be WC (writecombining) as the only current >> user (the NVMe CMB) was originally mapped WC before the P2PDMA code >> replaced the mapping with devm_memremap_pages(). > > Will the change to UC regress this existing use case?
I don't think so. They've been essentially mapped UC for a long time now (since the P2PDMA patch set was merged) and nobody has complained.
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