Messages in this thread | | | Date | Thu, 19 Mar 2020 17:24:39 +0100 | From | Joerg Roedel <> | Subject | Re: [PATCH 41/70] x86/sev-es: Add Runtime #VC Exception Handler |
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On Thu, Mar 19, 2020 at 08:44:03AM -0700, Andy Lutomirski wrote: > On Thu, Mar 19, 2020 at 2:14 AM Joerg Roedel <joro@8bytes.org> wrote: > > > > From: Tom Lendacky <thomas.lendacky@amd.com> > > > > Add the handler for #VC exceptions invoked at runtime. > > If I read this correctly, this does not use IST. If that's true, I > don't see how this can possibly work. There at least two nasty cases > that come to mind: > > 1. SYSCALL followed by NMI. The NMI IRET hack gets to #VC and we > explode. This is fixable by getting rid of the NMI EFLAGS.TF hack.
Not an issue in this patch-set, the confusion comes from the fact that I left some parts of the single-step-over-iret code in the patch. But it is not used. The NMI handling in this patch-set sends the NMI-complete message before the IRET, when the kernel is still in a safe environment (kernel stack, kernel cr3).
> 2. tools/testing/selftests/x86/mov_ss_trap_64. User code does MOV > (addr), SS; SYSCALL, where addr has a data breakpoint. We get #DB > promoted to #VC with no stack.
Also not an issue, as debugging is not supported at the moment in SEV-ES guests (hardware has no way yet to save/restore the debug registers across #VMEXITs). But this will change with future hardware. If you look at the implementation for dr7 read/write events, you see that the dr7 value is cached and returned, but does not make it to the hardware dr7.
I though about using IST for the #VC handler, but the implications for nesting #VC handlers made me decide against it. But for future hardware that supports debugging inside SEV-ES guests it will be an issue. I'll think about how to fix the problem, it probably has to be IST :(
Regards,
Joerg
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