Messages in this thread | | | Subject | Re: [PATCH v3 2/2] irqchip/gic-v3-its: Balance initial LPI affinity across CPUs | From | John Garry <> | Date | Wed, 18 Mar 2020 14:25:04 +0000 |
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On 18/03/2020 14:16, Marc Zyngier wrote: >> >> On my D06CS board (128 core), there seems to be something wrong, as >> the q0 affinity mask looks incorrect: >> >> PCI name is 81:00.0: nvme0n1 >> >> >> irq 322, cpu list 69, effective list 69 >> >>
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> > Sorry, can you explain in more detail what you find wrong in this log? > Is it that interrupt 322 has a single CPU affinity instead of a list? > >> And something stranger for my colleague Luo Jiaxing, specifically the
Hi Marc,
Sorry, ignore this. I just realized after that the NVMe PCI driver reserved queue0 vector as without affinity spreading, i.e. non-managed.
Cheers, John
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