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Subject[PATCH 14/28] dt-bindings: arm: l2x0: Tauros 3 is PL310 compatible
Date
The validation is unhappy about mmp3-dell-ariel declaring its
marvell,tauros3-cache node to be compatible with arm,pl310-cache:

mmp3-dell-ariel.dt.yaml: cache-controller@d0020000: compatible:
Additional items are not allowed ('arm,pl310-cache' was unexpected)
mmp3-dell-ariel.dt.yaml: cache-controller@d0020000: compatible:
['marvell,tauros3-cache', 'arm,pl310-cache'] is too long

Let's allow this -- Tauros 3 is designed to be compatible with PL310.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
---
.../devicetree/bindings/arm/l2c2x0.yaml | 45 ++++++++++---------
1 file changed, 24 insertions(+), 21 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.yaml b/Documentation/devicetree/bindings/arm/l2c2x0.yaml
index 913a8cd8b2c00..7e39088a9bed2 100644
--- a/Documentation/devicetree/bindings/arm/l2c2x0.yaml
+++ b/Documentation/devicetree/bindings/arm/l2c2x0.yaml
@@ -29,27 +29,30 @@ allOf:

properties:
compatible:
- enum:
- - arm,pl310-cache
- - arm,l220-cache
- - arm,l210-cache
- # DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
- - bcm,bcm11351-a2-pl310-cache
- # For Broadcom bcm11351 chipset where an
- # offset needs to be added to the address before passing down to the L2
- # cache controller
- - brcm,bcm11351-a2-pl310-cache
- # Marvell Controller designed to be
- # compatible with the ARM one, with system cache mode (meaning
- # maintenance operations on L1 are broadcasted to the L2 and L2
- # performs the same operation).
- - marvell,aurora-system-cache
- # Marvell Controller designed to be
- # compatible with the ARM one with outer cache mode.
- - marvell,aurora-outer-cache
- # Marvell Tauros3 cache controller, compatible
- # with arm,pl310-cache controller.
- - marvell,tauros3-cache
+ oneOf:
+ - enum:
+ - arm,pl310-cache
+ - arm,l220-cache
+ - arm,l210-cache
+ # DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
+ - bcm,bcm11351-a2-pl310-cache
+ # For Broadcom bcm11351 chipset where an
+ # offset needs to be added to the address before passing down to the L2
+ # cache controller
+ - brcm,bcm11351-a2-pl310-cache
+ # Marvell Controller designed to be
+ # compatible with the ARM one, with system cache mode (meaning
+ # maintenance operations on L1 are broadcasted to the L2 and L2
+ # performs the same operation).
+ - marvell,aurora-system-cache
+ # Marvell Controller designed to be
+ # compatible with the ARM one with outer cache mode.
+ - marvell,aurora-outer-cache
+ - items:
+ # Marvell Tauros3 cache controller, compatible
+ # with arm,pl310-cache controller.
+ - const: marvell,tauros3-cache
+ - const: arm,pl310-cache

cache-level:
const: 2
--
2.25.1
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