Messages in this thread | | | Subject | Re: [RFC PATCH v4 8/8] arm64: tegra: Add Tegra VI CSI support in device tree | From | Sowjanya Komatineni <> | Date | Sun, 15 Mar 2020 15:21:36 -0700 |
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On 3/15/20 5:54 AM, Dmitry Osipenko wrote: > External email: Use caution opening links or attachments > > > 15.03.2020 04:46, Sowjanya Komatineni пишет: >> Tegra210 contains VI controller for video input capture from MIPI >> CSI camera sensors and also supports built-in test pattern generator. >> >> CSI ports can be one-to-one mapped to VI channels for capturing from >> an external sensor or from built-in test pattern generator. >> >> This patch adds support for VI and CSI and enables them in Tegra210 >> device tree. >> >> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> >> --- > Hello Sowjanya, > > ... >> + >> + pd_venc: venc { >> + clocks = <&tegra_car TEGRA210_CLK_VI>, >> + <&tegra_car TEGRA210_CLK_CSI>; >> + resets = <&tegra_car 20>, > What is the clock #20?
Hi Dmitry,
20 is VI_RST not defined in include/dt-bindings/reset/tegra210-car.h
Will add define and will fix to use it.
>> + <&tegra_car TEGRA210_CLK_CSI>, >> + <&mc TEGRA210_MC_RESET_VI>; > Does this order means that memory controller will be reset *after* > resetting the CSI/VI hardware? This is incorrect reset sequence. > > The memory controller reset should be kept asserted during of the time > of the hardware resetting procedure. > > The correct sequence should be as follows: > > 1. Assert MC > 2. Reset VI > 3. Deassert MC Right, will fix order. Thanks
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