Messages in this thread | | | From | David Laight <> | Subject | RE: [PATCH v8 01/12] clk: pwm: Use 64-bit division function | Date | Wed, 11 Mar 2020 16:58:24 +0000 |
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From: Guru Das Srinagesh > Sent: 11 March 2020 01:41 > > Since the PWM framework is switching struct pwm_args.period's datatype > to u64, prepare for this transition by using div64_u64 to handle a > 64-bit divisor. > > Cc: Michael Turquette <mturquette@baylibre.com> > Cc: Stephen Boyd <sboyd@kernel.org> > Cc: linux-clk@vger.kernel.org > > Signed-off-by: Guru Das Srinagesh <gurus@codeaurora.org> > --- > drivers/clk/clk-pwm.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/clk-pwm.c b/drivers/clk/clk-pwm.c > index 87fe0b0e..7b1f7a0 100644 > --- a/drivers/clk/clk-pwm.c > +++ b/drivers/clk/clk-pwm.c > @@ -89,7 +89,7 @@ static int clk_pwm_probe(struct platform_device *pdev) > } > > if (of_property_read_u32(node, "clock-frequency", &clk_pwm->fixed_rate)) > - clk_pwm->fixed_rate = NSEC_PER_SEC / pargs.period; > + clk_pwm->fixed_rate = div64_u64(NSEC_PER_SEC, pargs.period);
That cannot be needed, a 32 bit division is fine. More interesting would be whether pargs.period is sane (eg not zero). I'd assign pargs.period to an 'unsigned int' variable prior to the division (I hate casts - been bitten by them in the past.).
> > if (pargs.period != NSEC_PER_SEC / clk_pwm->fixed_rate && > pargs.period != DIV_ROUND_UP(NSEC_PER_SEC, clk_pwm->fixed_rate)) { > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project
David
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