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SubjectRe: [PATCH 2/3] ARM: dts: sun8i: r40: Fix register base address for SPI2 and SPI3
On Wed, 11 Mar 2020 01:47:08 +0800
Chen-Yu Tsai <wens@kernel.org> wrote:

Hi Chen-Yu,

sorry, didn't spot this before posting my version!

> From: Chen-Yu Tsai <wens@csie.org>
>
> When the SPI device nodes were added, SPI2 and SPI3 had incorrect
> register base addresses.
>
> Fix the base address for both of them.
>
> Fixes: 554581b79139 ("ARM: dts: sun8i: R40: Add SPI controllers nodes and pinmuxes")
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

As you suggested, it would be nice to add Juan's reported by, since he reported this before:
https://groups.google.com/forum/#!topic/linux-sunxi/5ZzkDXx2F-M

Cheers,
Andre

> ---
> arch/arm/boot/dts/sun8i-r40.dtsi | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
> index b278686d0c22..81cc92ddc78b 100644
> --- a/arch/arm/boot/dts/sun8i-r40.dtsi
> +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
> @@ -718,10 +718,10 @@ spi1: spi@1c06000 {
> #size-cells = <0>;
> };
>
> - spi2: spi@1c07000 {
> + spi2: spi@1c17000 {
> compatible = "allwinner,sun8i-r40-spi",
> "allwinner,sun8i-h3-spi";
> - reg = <0x01c07000 0x1000>;
> + reg = <0x01c17000 0x1000>;
> interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>;
> clock-names = "ahb", "mod";
> @@ -731,10 +731,10 @@ spi2: spi@1c07000 {
> #size-cells = <0>;
> };
>
> - spi3: spi@1c0f000 {
> + spi3: spi@1c1f000 {
> compatible = "allwinner,sun8i-r40-spi",
> "allwinner,sun8i-h3-spi";
> - reg = <0x01c0f000 0x1000>;
> + reg = <0x01c1f000 0x1000>;
> interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>;
> clock-names = "ahb", "mod";

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