Messages in this thread | | | From | "Z.q. Hou" <> | Subject | RE: [PATCHv7] arm64: dts: ls1028a: Add PCIe controller DT nodes | Date | Wed, 11 Mar 2020 09:50:29 +0000 |
| |
Hi Shawn,
Thanks a lot for your comments!
> -----Original Message----- > From: Shawn Guo <shawnguo@kernel.org> > Sent: 2020年3月11日 16:21 > To: Z.q. Hou <zhiqiang.hou@nxp.com> > Cc: devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; > robh+dt@kernel.org; michael@walle.cc; Leo Li <leoyang.li@nxp.com>; > Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian <minghuan.lian@nxp.com>; > Xiaowei Bao <xiaowei.bao@nxp.com> > Subject: Re: [PATCHv7] arm64: dts: ls1028a: Add PCIe controller DT nodes > > On Mon, Mar 02, 2020 at 12:23:05PM +0800, Zhiqiang Hou wrote: > > From: Xiaowei Bao <xiaowei.bao@nxp.com> > > > > LS1028a implements 2 PCIe 3.0 controllers. > > > > Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > Tested-by: Michael Walle <michael@walle.cc> > > --- > > V7: > > - Rebased the patch to the latest code base. > > - Added property 'iommu-map'. > > > > .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 54 > +++++++++++++++++++ > > 1 file changed, 54 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi > b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi > > index 41c9633293fb..3f31641dcced 100644 > > --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi > > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi > > @@ -717,6 +717,60 @@ > > #thermal-sensor-cells = <1>; > > }; > > > > + pcie@3400000 { > > Please keep nodes sorted in unit-address.
OK, will correct in next version.
Thanks, Zhiqiang
> > Shawn > > > + compatible = "fsl,ls1028a-pcie"; > > + reg = <0x00 0x03400000 0x0 0x00100000 /* controller > registers */ > > + 0x80 0x00000000 0x0 0x00002000>; /* configuration > space */ > > + reg-names = "regs", "config"; > > + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME > interrupt */ > > + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer > interrupt */ > > + interrupt-names = "pme", "aer"; > > + #address-cells = <3>; > > + #size-cells = <2>; > > + device_type = "pci"; > > + dma-coherent; > > + num-viewport = <8>; > > + bus-range = <0x0 0xff>; > > + ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 > 0x00010000 /* downstream I/O */ > > + 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 > 0x40000000>; /* non-prefetchable memory */ > > + msi-parent = <&its>; > > + #interrupt-cells = <1>; > > + interrupt-map-mask = <0 0 0 7>; > > + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 > IRQ_TYPE_LEVEL_HIGH>, > > + <0000 0 0 2 &gic 0 0 GIC_SPI 110 > IRQ_TYPE_LEVEL_HIGH>, > > + <0000 0 0 3 &gic 0 0 GIC_SPI 111 > IRQ_TYPE_LEVEL_HIGH>, > > + <0000 0 0 4 &gic 0 0 GIC_SPI 112 > IRQ_TYPE_LEVEL_HIGH>; > > + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ > > + status = "disabled"; > > + }; > > + > > + pcie@3500000 { > > + compatible = "fsl,ls1028a-pcie"; > > + reg = <0x00 0x03500000 0x0 0x00100000 /* controller > registers */ > > + 0x88 0x00000000 0x0 0x00002000>; /* configuration > space */ > > + reg-names = "regs", "config"; > > + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-names = "pme", "aer"; > > + #address-cells = <3>; > > + #size-cells = <2>; > > + device_type = "pci"; > > + dma-coherent; > > + num-viewport = <8>; > > + bus-range = <0x0 0xff>; > > + ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 > 0x00010000 /* downstream I/O */ > > + 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 > 0x40000000>; /* non-prefetchable memory */ > > + msi-parent = <&its>; > > + #interrupt-cells = <1>; > > + interrupt-map-mask = <0 0 0 7>; > > + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 > IRQ_TYPE_LEVEL_HIGH>, > > + <0000 0 0 2 &gic 0 0 GIC_SPI 115 > IRQ_TYPE_LEVEL_HIGH>, > > + <0000 0 0 3 &gic 0 0 GIC_SPI 116 > IRQ_TYPE_LEVEL_HIGH>, > > + <0000 0 0 4 &gic 0 0 GIC_SPI 117 > IRQ_TYPE_LEVEL_HIGH>; > > + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ > > + status = "disabled"; > > + }; > > + > > pcie@1f0000000 { /* Integrated Endpoint Root Complex */ > > compatible = "pci-host-ecam-generic"; > > reg = <0x01 0xf0000000 0x0 0x100000>; > > -- > > 2.17.1 > >
| |