Messages in this thread | | | Date | Wed, 11 Mar 2020 09:45:15 +0100 | From | Robert Richter <> | Subject | Re: [PATCH v3 03/32] irqchip/gic-v3: Workaround Cavium TX1 erratum when reading GICD_TYPER2 |
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Hi Marc,
On 10.03.20 11:41:09, Marc Zyngier wrote: > On 2020-03-09 22:11, Robert Richter wrote: > > On 24.12.19 11:10:26, Marc Zyngier wrote:
> > > @@ -1502,6 +1512,12 @@ static const struct gic_quirk gic_quirks[] = { > > > .mask = 0xffffffff, > > > .init = gic_enable_quirk_hip06_07, > > > }, > > > + { > > > + .desc = "GICv3: Cavium TX1 GICD_TYPER2 erratum", > > > > There is no errata number yet. > > Please let me know when/if you obtain one.
GIC-38539: GIC faults when accessing reserved GICD_TYPER2 register
Applies to (covered with iidr mask below):
ThunderX: CN88xx OCTEON TX: CN83xx, CN81xx OCTEON TX2: CN93xx, CN96xx, CN98xx, CNF95xx*
Issue: Access to GIC reserved registers results in an exception. Notes: 1) This applies to other reserved registers too. 2) The errata number is unique over all IP blocks, so a macro CAVIUM_ERRATUM_38539 is ok.
> > > > > > + .iidr = 0xa100034c, > > > + .mask = 0xfff00fff, > > > + .init = gic_enable_quirk_tx1, > > > > All TX1 and OcteonTX parts are affected, which is a0-a7 and b0-b7. So > > the iidr/mask should be: > > > > .iidr = 0xa000034c, > > .mask = 0xe8f00fff, > > Thanks, that's pretty helpful. I'll update the patch with these values > and the corresponding description. > > > > + }, > > > { > > > } > > > };
Thank you for addressing this.
-Robert
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