Messages in this thread | | | Date | Tue, 10 Mar 2020 14:04:35 +0800 | From | Shawn Guo <> | Subject | Re: [PATCH v2 05/14] clk: imx: pfdv2: determine best parent rate |
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On Wed, Feb 19, 2020 at 03:59:48PM +0800, peng.fan@nxp.com wrote: > From: Peng Fan <peng.fan@nxp.com> > > pfdv2 is only used in i.MX7ULP. To get best pfd output, the i.MX7ULP > Datasheet defines two best PLL rate and pfd frac. > > Per Datasheel > All PLLs on i.MX 7ULP either have VCO base frequency of > 480 MHz or 528 MHz. So when determine best rate, we also > determine best parent rate which could match the requirement. > > For some reason the current parent might not be 480MHz or 528MHz, > so we still take current parent rate as a choice. > > And we also enable flag CLK_SET_RATE_PARENT to let parent rate > to be configured. > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
Applied, thanks.
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