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    Subject[PATCH v2 09/13] dt-bindings: arm: Convert Calxeda L2 cache controller to json-schema
    Date
    Convert the L2-ECC controller binding to DT schema format using
    json-schema.
    This is indented to be just used for error reporting.

    Signed-off-by: Andre Przywara <andre.przywara@arm.com>
    ---
    .../devicetree/bindings/arm/calxeda/l2ecc.txt | 15 -------
    .../bindings/arm/calxeda/l2ecc.yaml | 43 +++++++++++++++++++
    2 files changed, 43 insertions(+), 15 deletions(-)
    delete mode 100644 Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt
    create mode 100644 Documentation/devicetree/bindings/arm/calxeda/l2ecc.yaml

    diff --git a/Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt b/Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt
    deleted file mode 100644
    index 94e642a33db0..000000000000
    --- a/Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt
    +++ /dev/null
    @@ -1,15 +0,0 @@
    -Calxeda Highbank L2 cache ECC
    -
    -Properties:
    -- compatible : Should be "calxeda,hb-sregs-l2-ecc"
    -- reg : Address and size for ECC error interrupt clear registers.
    -- interrupts : Should be single bit error interrupt, then double bit error
    - interrupt.
    -
    -Example:
    -
    - sregs@fff3c200 {
    - compatible = "calxeda,hb-sregs-l2-ecc";
    - reg = <0xfff3c200 0x100>;
    - interrupts = <0 71 4 0 72 4>;
    - };
    diff --git a/Documentation/devicetree/bindings/arm/calxeda/l2ecc.yaml b/Documentation/devicetree/bindings/arm/calxeda/l2ecc.yaml
    new file mode 100644
    index 000000000000..5481dd7216ba
    --- /dev/null
    +++ b/Documentation/devicetree/bindings/arm/calxeda/l2ecc.yaml
    @@ -0,0 +1,43 @@
    +# SPDX-License-Identifier: GPL-2.0
    +%YAML 1.2
    +---
    +$id: http://devicetree.org/schemas/arm/calxeda/l2ecc.yaml#
    +$schema: http://devicetree.org/meta-schemas/core.yaml#
    +
    +title: Calxeda Highbank L2 cache ECC
    +
    +description: |
    + Binding for the Calxeda Highbank L2 cache controller ECC device.
    + This does not cover the actual L2 cache controller control registers,
    + but just the error reporting functionality.
    +
    +maintainers:
    + - Andre Przywara <andre.przywara@arm.com>
    +
    +properties:
    + compatible:
    + const: "calxeda,hb-sregs-l2-ecc"
    +
    + reg:
    + maxItems: 1
    +
    + interrupts:
    + description: |
    + Should be single bit error interrupt, then double bit error interrupt.
    + minItems: 2
    + maxItems: 2
    +
    +required:
    + - compatible
    + - reg
    + - interrupts
    +
    +additionalProperties: false
    +
    +examples:
    + - |
    + sregs@fff3c200 {
    + compatible = "calxeda,hb-sregs-l2-ecc";
    + reg = <0xfff3c200 0x100>;
    + interrupts = <0 71 4>, <0 72 4>;
    + };
    --
    2.17.1
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