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SubjectRe: [PATCH] ARM: use assembly mnemonics for VFP register access
On Tue, Feb 25, 2020 at 11:33 AM Ard Biesheuvel
<ard.biesheuvel@linaro.org> wrote:
>
> On Tue, 25 Feb 2020 at 20:10, Nick Desaulniers <ndesaulniers@google.com> wrote:
> > Ah, this is only when streaming to assembly. Looks like they have the
> > same encoding, and produce the same disassembly. (Godbolt emits
> > assembly by default, and has the option to compile, then disassemble).
> > If I take my case from godbolt above:
> >
> > ➜ /tmp arm-linux-gnueabihf-gcc -O2 -c x.c
> > ➜ /tmp llvm-objdump -dr x.o
> >
> > x.o: file format elf32-arm-little
> >
> >
> > Disassembly of section .text:
> >
> > 00000000 bar:
> > 0: f1 ee 10 0a vmrs r0, fpscr
> > 4: 70 47 bx lr
> > 6: 00 bf nop
> >
> > 00000008 baz:
> > 8: f1 ee 10 0a vmrs r0, fpscr
> > c: 70 47 bx lr
> > e: 00 bf nop
> >
> > So indeed a similar encoding exists for the two different assembler
> > instructions.
>
> Does that hold for ARM (A32) instructions as well?

TIL -mthumb is the default for arm-linux-gnueabihf-gcc -O2.

➜ /tmp arm-linux-gnueabihf-gcc -O2 -c x.c -marm
➜ /tmp llvm-objdump -dr x.o

x.o: file format elf32-arm-little


Disassembly of section .text:

00000000 bar:
0: 10 0a f1 ee vmrs r0, fpscr
4: 1e ff 2f e1 bx lr

00000008 baz:
8: 10 0a f1 ee vmrs r0, fpscr
c: 1e ff 2f e1 bx lr

^ Just to show the matching encoding.
--
Thanks,
~Nick Desaulniers

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