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SubjectRe: [PATCH 3/3] clk: imx8mp: Correct the enet_qos parent clock
On Wed, Feb 19, 2020 at 02:04:11PM +0800, Anson Huang wrote:
> From: Fugang Duan <fugang.duan@nxp.com>
>
> enet_qos is for eqos tsn AXI bus clock whose clock source is from
> ccm_enet_axi_clk_root, and controlled by CCM_CCGR59(offset 0x43b0)
> and CCM_CCGR64(offset 0x4400), so correct enet_qos root clock's
> parent clock to sim_enet.
>
> Fixes: 9c140d992676 ("clk: imx: Add support for i.MX8MP clock driver")
> Signed-off-by: Fugang Duan <fugang.duan@nxp.com>

When you forward a patch from someone, you need to add your SoB.

I fixed it up and applied all.

Shawn

> ---
> drivers/clk/imx/clk-imx8mp.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
> index 1a9d7a0..cb58fb8 100644
> --- a/drivers/clk/imx/clk-imx8mp.c
> +++ b/drivers/clk/imx/clk-imx8mp.c
> @@ -688,7 +688,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
> hws[IMX8MP_CLK_CAN1_ROOT] = imx_clk_hw_gate2("can1_root_clk", "can1", ccm_base + 0x4350, 0);
> hws[IMX8MP_CLK_CAN2_ROOT] = imx_clk_hw_gate2("can2_root_clk", "can2", ccm_base + 0x4360, 0);
> hws[IMX8MP_CLK_SDMA1_ROOT] = imx_clk_hw_gate4("sdma1_root_clk", "ipg_root", ccm_base + 0x43a0, 0);
> - hws[IMX8MP_CLK_ENET_QOS_ROOT] = imx_clk_hw_gate4("enet_qos_root_clk", "enet_axi", ccm_base + 0x43b0, 0);
> + hws[IMX8MP_CLK_ENET_QOS_ROOT] = imx_clk_hw_gate4("enet_qos_root_clk", "sim_enet_root_clk", ccm_base + 0x43b0, 0);
> hws[IMX8MP_CLK_SIM_ENET_ROOT] = imx_clk_hw_gate4("sim_enet_root_clk", "enet_axi", ccm_base + 0x4400, 0);
> hws[IMX8MP_CLK_GPU2D_ROOT] = imx_clk_hw_gate4("gpu2d_root_clk", "gpu2d_div", ccm_base + 0x4450, 0);
> hws[IMX8MP_CLK_GPU3D_ROOT] = imx_clk_hw_gate4("gpu3d_root_clk", "gpu3d_core_div", ccm_base + 0x4460, 0);
> --
> 2.7.4
>

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