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Subject[PATCH] irqchip/gic-v3-its: Clear Valid before writing any bits else in VPENDBASER
Date
The Valid bit must be cleared before changing anything else when writing
GICR_VPENDBASER to avoid the UNPREDICTABLE behavior. This is exactly what
we've done on 32bit arm, but not on arm64.

This works fine on GICv4 where we only clear Valid for a vPE deschedule.
With the introduction of GICv4.1, we might also need to talk something else
(e.g., PendingLast, Doorbell) to the redistributor when clearing the Valid.
Let's port the 32bit gicr_write_vpendbaser() to arm64 so that hardware can
do the right thing after descheduling the vPE.

Cc: Yanlei Jia <jiayanlei@huawei.com>
Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
---
arch/arm64/include/asm/arch_gicv3.h | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h
index 25fec4bde43a..effe66e1ca58 100644
--- a/arch/arm64/include/asm/arch_gicv3.h
+++ b/arch/arm64/include/asm/arch_gicv3.h
@@ -143,7 +143,18 @@ static inline u32 gic_read_rpr(void)
#define gicr_write_vpropbaser(v, c) writeq_relaxed(v, c)
#define gicr_read_vpropbaser(c) readq_relaxed(c)

-#define gicr_write_vpendbaser(v, c) writeq_relaxed(v, c)
+#define gicr_write_vpendbaser(v, c) do { \
+ u64 tmp = readq_relaxed(c); \
+ \
+ /* Clear Valid before writing any bits else. */ \
+ if (tmp & GICR_VPENDBASER_Valid) { \
+ tmp &= ~GICR_VPENDBASER_Valid; \
+ writeq_relaxed(tmp, c); \
+ } \
+ \
+ writeq_relaxed(v, c); \
+} while (0)
+
#define gicr_read_vpendbaser(c) readq_relaxed(c)

static inline bool gic_prio_masking_enabled(void)
--
2.19.1

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