Messages in this thread | | | Date | Sat, 22 Feb 2020 00:47:39 +0800 | Subject | Re: Questions about logic_pio | From | Jiaxun Yang <> |
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于 2020年2月21日 GMT+08:00 下午7:49:45, John Garry <john.garry@huawei.com> 写到: >On 21/02/2020 00:42, Jiaxun Yang wrote: >> > >> > I will add this may not cover your need, as you probably cannot >deal >> > with any logical PIO <-> ISA translation without modifying the >device >> > driver. For this, we may need to reserve the first 0x4000 in >logical PIO >> > space for this sort of legacy host. >> >> Hi, >> >> After thinking twice, I realized that the most convenient way for me >is >> adding an option to get rid of the mess of logic PIO. MIPS system is >emulating >> x86's behavior, while logic PIO isn't designed for such platform. > >It was designed for archs which define PCI_IOBASE for PCI MMIO-based or > >IndirectIO-based IO port access. > >> >> Or probably I need a variation of Logic PIO, which leave MMIO space >AS-IS >> (not try to reallocate it) > >That does not work if add a PCI host with MMIO-based IO port regions >into the mix. > >It only so happens today that for mips you have a single MMIO-based IO >port region, and you have IO port base for that region conveniently @ >0x0. Then your drivers can have fixed IO port addresses.
In MIPS, PCI Host Bridge share PIO region with legacy devices.
Probably the better solution is to add a kind of logic pio region called FIXED_MMIO, so we can occupy some low ioports for these fixed devices at boot time.
A ISA bridge node in DeviceTree can be used to express this region.
I'm going to work on this and try to make a RFC patch later.
Thanks for your help again! > >For dealing with multiple MMIO-based IO ports regions - which is the >case for PCI host bridges - then you need to map those MMIO-based IO >port regions to different regions in IO port space. > >> but still preserving higher 0x4000 for indirect access. > >Then there is no space for PCI MMIO-based IO ports.
Well, it can be higher or lower, whatever.
> >> >> Thanks a lot! >> > >> > That would not be a bad thing - see >> >>https://lore.kernel.org/linux-pci/1560262374-67875-1-git-send-email-john.garry@huawei.com/ >> > >> > >> > > >> > > This driver deals with legacy IO ports where we need to bitbang
-- Jiaxun Yang
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