Messages in this thread | | | From | Yash Shah <> | Subject | [PATCH v5 0/2] cacheinfo support to read no. of L2 cache ways enabled | Date | Thu, 20 Feb 2020 10:45:17 +0530 |
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The patchset includes 2 patches. Patch 1 implements cache_get_priv_group which make use of a generic ops structure to return a private attribute group for custom cacheinfo. Patch 2 implements a private attribute named "number_of_ways_enabled" in the cacheinfo framework. Reading this attribute returns the number of L2 cache ways enabled at runtime,
This patchset is based on Linux v5.6-rc2 and tested on HiFive Unleashed board.
v5: - Since WayEnable is 8bits, mask out and return only the last 8 bit in l2_largest_wayenabled() - Rebased on Linux v5.6-rc2
v4: - Rename "sifive_l2_largest_wayenabled" to "l2_largest_wayenabled" and make it a static function
v3: - As per Anup Patel's suggestion[0], implement a new approach which uses generic ops structure. Hence addition of patch 1 to this series and corresponding changes to patch 2. - Dropped "riscv: dts: Add DT support for SiFive L2 cache controller" patch since it is already merged - Rebased on Linux v5.5-rc6
Changes in v2: - Rebase the series on v5.5-rc3 - Remove the reserved-memory node from DT
[0]: https://lore.kernel.org/linux-riscv/CAAhSdy0CXde5s_ya=4YvmA4UQ5f5gLU-Z_FaOr8LPni+s_615Q@mail.gmail.com/
Yash Shah (2): riscv: cacheinfo: Implement cache_get_priv_group with a generic ops structure riscv: Add support to determine no. of L2 cache way enabled
arch/riscv/include/asm/cacheinfo.h | 15 ++++++++++++++ arch/riscv/kernel/cacheinfo.c | 17 ++++++++++++++++ drivers/soc/sifive/sifive_l2_cache.c | 38 ++++++++++++++++++++++++++++++++++++ 3 files changed, 70 insertions(+) create mode 100644 arch/riscv/include/asm/cacheinfo.h
-- 2.7.4
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