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    Subject[PATCH 5.5 63/80] perf/x86/intel: Fix inaccurate period in context switch for auto-reload
    Date
    From: Kan Liang <kan.liang@linux.intel.com>

    commit f861854e1b435b27197417f6f90d87188003cb24 upstream.

    Perf doesn't take the left period into account when auto-reload is
    enabled with fixed period sampling mode in context switch.

    Here is the MSR trace of the perf command as below.
    (The MSR trace is simplified from a ftrace log.)

    #perf record -e cycles:p -c 2000000 -- ./triad_loop

    //The MSR trace of task schedule out
    //perf disable all counters, disable PEBS, disable GP counter 0,
    //read GP counter 0, and re-enable all counters.
    //The counter 0 stops at 0xfffffff82840
    write_msr: MSR_CORE_PERF_GLOBAL_CTRL(38f), value 0
    write_msr: MSR_IA32_PEBS_ENABLE(3f1), value 0
    write_msr: MSR_P6_EVNTSEL0(186), value 40003003c
    rdpmc: 0, value fffffff82840
    write_msr: MSR_CORE_PERF_GLOBAL_CTRL(38f), value f000000ff

    //The MSR trace of the same task schedule in again
    //perf disable all counters, enable and set GP counter 0,
    //enable PEBS, and re-enable all counters.
    //0xffffffe17b80 (-2000000) is written to GP counter 0.
    write_msr: MSR_CORE_PERF_GLOBAL_CTRL(38f), value 0
    write_msr: MSR_IA32_PMC0(4c1), value ffffffe17b80
    write_msr: MSR_P6_EVNTSEL0(186), value 40043003c
    write_msr: MSR_IA32_PEBS_ENABLE(3f1), value 1
    write_msr: MSR_CORE_PERF_GLOBAL_CTRL(38f), value f000000ff

    When the same task schedule in again, the counter should starts from
    previous left. However, it starts from the fixed period -2000000 again.

    A special variant of intel_pmu_save_and_restart() is used for
    auto-reload, which doesn't update the hwc->period_left.
    When the monitored task schedules in again, perf doesn't know the left
    period. The fixed period is used, which is inaccurate.

    With auto-reload, the counter always has a negative counter value. So
    the left period is -value. Update the period_left in
    intel_pmu_save_and_restart_reload().

    With the patch:

    //The MSR trace of task schedule out
    write_msr: MSR_CORE_PERF_GLOBAL_CTRL(38f), value 0
    write_msr: MSR_IA32_PEBS_ENABLE(3f1), value 0
    write_msr: MSR_P6_EVNTSEL0(186), value 40003003c
    rdpmc: 0, value ffffffe25cbc
    write_msr: MSR_CORE_PERF_GLOBAL_CTRL(38f), value f000000ff

    //The MSR trace of the same task schedule in again
    write_msr: MSR_CORE_PERF_GLOBAL_CTRL(38f), value 0
    write_msr: MSR_IA32_PMC0(4c1), value ffffffe25cbc
    write_msr: MSR_P6_EVNTSEL0(186), value 40043003c
    write_msr: MSR_IA32_PEBS_ENABLE(3f1), value 1
    write_msr: MSR_CORE_PERF_GLOBAL_CTRL(38f), value f000000ff

    Fixes: d31fc13fdcb2 ("perf/x86/intel: Fix event update for auto-reload")
    Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
    Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
    Signed-off-by: Ingo Molnar <mingo@kernel.org>
    Link: https://lkml.kernel.org/r/20200121190125.3389-1-kan.liang@linux.intel.com
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    arch/x86/events/intel/ds.c | 2 ++
    1 file changed, 2 insertions(+)

    --- a/arch/x86/events/intel/ds.c
    +++ b/arch/x86/events/intel/ds.c
    @@ -1713,6 +1713,8 @@ intel_pmu_save_and_restart_reload(struct
    old = ((s64)(prev_raw_count << shift) >> shift);
    local64_add(new - old + count * period, &event->count);

    + local64_set(&hwc->period_left, -new);
    +
    perf_event_update_userpage(event);

    return 0;

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