lkml.org 
[lkml]   [2020]   [Feb]   [15]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
From
SubjectRe: [PATCH 0/2] Add boot interrupt quirk mechanism for Xeon chipsets
Date
Thomas Gleixner <tglx@linutronix.de> writes:

> Sean V Kelley <sean.v.kelley@linux.intel.com> writes:
>> When IRQ lines on secondary or higher IO-APICs are masked (e.g.,
>> Real-Time threaded interrupts), many chipsets redirect IRQs on
>> this line to the legacy PCH and in turn the base IO-APIC in the
>> system. The unhandled interrupts on the base IO-APIC will be
>> identified by the Linux kernel as Spurious Interrupts and can
>> lead to disabled IRQ lines.
>>
>> Disabling this legacy PCI interrupt routing is chipset-specific and
>> varies in mechanism between chipset vendors and across generations.
>> In some cases the mechanism is exposed to BIOS but not all BIOS
>> vendors choose to pick it up. With the increasing usage of RT as it
>> marches towards mainline, additional issues have been raised with
>> more recent Xeon chipsets.
>>
>> This patchset disables the boot interrupt on these Xeon chipsets where
>> this is possible with an additional mechanism. In addition, this
>> patchset includes documentation covering the background of this quirk.
>
> Well done! The documentation is really appreciated!
>
> Reviewed-by: Thomas Gleixner <tglx@linutronix.de>

Bjorn, this should go into stable as well IMO.

Thanks,

tglx

\
 
 \ /
  Last update: 2020-02-15 10:26    [W:0.034 / U:0.060 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site