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    Subject[PATCH AUTOSEL 5.4 173/459] ARM: dts: imx6: rdu2: Disable WP for USDHC2 and USDHC3
    Date
    From: Andrey Smirnov <andrew.smirnov@gmail.com>

    [ Upstream commit cd58a174e58649426fb43d7456e5f7d7eab58af1 ]

    RDU2 production units come with resistor connecting WP pin to
    correpsonding GPIO DNPed for both SD card slots. Drop any WP related
    configuration and mark both slots with "disable-wp".

    Reported-by: Chris Healy <cphealy@gmail.com>
    Reviewed-by: Chris Healy <cphealy@gmail.com>
    Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
    Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
    Cc: Shawn Guo <shawnguo@kernel.org>
    Cc: Fabio Estevam <festevam@gmail.com>
    Cc: Lucas Stach <l.stach@pengutronix.de>
    Cc: linux-arm-kernel@lists.infradead.org
    Cc: linux-kernel@vger.kernel.org
    Signed-off-by: Shawn Guo <shawnguo@kernel.org>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi | 6 ++----
    1 file changed, 2 insertions(+), 4 deletions(-)

    diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
    index 93be00a60c887..7b5c0e9b0fcff 100644
    --- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
    +++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
    @@ -627,7 +627,7 @@
    pinctrl-0 = <&pinctrl_usdhc2>;
    bus-width = <4>;
    cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
    - wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
    + disable-wp;
    vmmc-supply = <&reg_3p3v_sd>;
    vqmmc-supply = <&reg_3p3v>;
    no-1-8-v;
    @@ -640,7 +640,7 @@
    pinctrl-0 = <&pinctrl_usdhc3>;
    bus-width = <4>;
    cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
    - wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
    + disable-wp;
    vmmc-supply = <&reg_3p3v_sd>;
    vqmmc-supply = <&reg_3p3v>;
    no-1-8-v;
    @@ -1055,7 +1055,6 @@
    MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
    MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
    MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
    - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x40010040
    MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x40010040
    >;
    };
    @@ -1068,7 +1067,6 @@
    MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
    MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
    MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
    - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x40010040
    MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x40010040

    >;
    --
    2.20.1
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