lkml.org 
[lkml]   [2020]   [Feb]   [14]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH AUTOSEL 5.4 075/459] clk: ti: dra7: fix parent for gmac_clkctrl
    Date
    From: Grygorii Strashko <grygorii.strashko@ti.com>

    [ Upstream commit 69e300283796dae7e8c2e6acdabcd31336c0c93e ]

    The parent clk for gmac clk ctrl has to be gmac_main_clk (125MHz) instead
    of dpll_gmac_ck (1GHz). This is caused incorrect CPSW MDIO operation.
    Hence, fix it.

    Fixes: dffa9051d546 ('clk: ti: dra7: add new clkctrl data')
    Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
    Signed-off-by: Tero Kristo <t-kristo@ti.com>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/clk/ti/clk-7xx.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
    index 9dd6185a4b4e2..66e4b2b9ec600 100644
    --- a/drivers/clk/ti/clk-7xx.c
    +++ b/drivers/clk/ti/clk-7xx.c
    @@ -405,7 +405,7 @@ static const struct omap_clkctrl_bit_data dra7_gmac_bit_data[] __initconst = {
    };

    static const struct omap_clkctrl_reg_data dra7_gmac_clkctrl_regs[] __initconst = {
    - { DRA7_GMAC_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "dpll_gmac_ck" },
    + { DRA7_GMAC_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "gmac_main_clk" },
    { 0 },
    };

    --
    2.20.1
    \
     
     \ /
      Last update: 2020-02-14 17:04    [W:4.053 / U:0.116 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site