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    Subject[PATCH AUTOSEL 5.4 171/459] clk: imx: Add correct failure handling for clk based helpers
    Date
    From: Abel Vesa <abel.vesa@nxp.com>

    [ Upstream commit f60f1c62c3188fcca945581e35e3440ee3fdcc95 ]

    If the clk_hw based API returns an error, trying to return the clk from
    hw will end up in a NULL pointer dereference. So adding the to_clk
    checker and using it inside every clk based macro helper we handle that
    case correctly.

    This to_clk is also temporary and will go away along with the clk based
    macro helpers once there is no user that need them anymore.

    Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
    Signed-off-by: Shawn Guo <shawnguo@kernel.org>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/clk/imx/clk.h | 37 ++++++++++++++++++++++---------------
    1 file changed, 22 insertions(+), 15 deletions(-)

    diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
    index f7a389a50401a..6fe64ff8ffa12 100644
    --- a/drivers/clk/imx/clk.h
    +++ b/drivers/clk/imx/clk.h
    @@ -51,48 +51,48 @@ struct imx_pll14xx_clk {
    };

    #define imx_clk_cpu(name, parent_name, div, mux, pll, step) \
    - imx_clk_hw_cpu(name, parent_name, div, mux, pll, step)->clk
    + to_clk(imx_clk_hw_cpu(name, parent_name, div, mux, pll, step))

    #define clk_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
    cgr_val, clk_gate_flags, lock, share_count) \
    - clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
    - cgr_val, clk_gate_flags, lock, share_count)->clk
    + to_clk(clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
    + cgr_val, clk_gate_flags, lock, share_count))

    #define imx_clk_pllv3(type, name, parent_name, base, div_mask) \
    - imx_clk_hw_pllv3(type, name, parent_name, base, div_mask)->clk
    + to_clk(imx_clk_hw_pllv3(type, name, parent_name, base, div_mask))

    #define imx_clk_pfd(name, parent_name, reg, idx) \
    - imx_clk_hw_pfd(name, parent_name, reg, idx)->clk
    + to_clk(imx_clk_hw_pfd(name, parent_name, reg, idx))

    #define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) \
    - imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask)->clk
    + to_clk(imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask))

    #define imx_clk_fixed_factor(name, parent, mult, div) \
    - imx_clk_hw_fixed_factor(name, parent, mult, div)->clk
    + to_clk(imx_clk_hw_fixed_factor(name, parent, mult, div))

    #define imx_clk_divider2(name, parent, reg, shift, width) \
    - imx_clk_hw_divider2(name, parent, reg, shift, width)->clk
    + to_clk(imx_clk_hw_divider2(name, parent, reg, shift, width))

    #define imx_clk_gate_dis(name, parent, reg, shift) \
    - imx_clk_hw_gate_dis(name, parent, reg, shift)->clk
    + to_clk(imx_clk_hw_gate_dis(name, parent, reg, shift))

    #define imx_clk_gate2(name, parent, reg, shift) \
    - imx_clk_hw_gate2(name, parent, reg, shift)->clk
    + to_clk(imx_clk_hw_gate2(name, parent, reg, shift))

    #define imx_clk_gate2_flags(name, parent, reg, shift, flags) \
    - imx_clk_hw_gate2_flags(name, parent, reg, shift, flags)->clk
    + to_clk(imx_clk_hw_gate2_flags(name, parent, reg, shift, flags))

    #define imx_clk_gate2_shared2(name, parent, reg, shift, share_count) \
    - imx_clk_hw_gate2_shared2(name, parent, reg, shift, share_count)->clk
    + to_clk(imx_clk_hw_gate2_shared2(name, parent, reg, shift, share_count))

    #define imx_clk_gate3(name, parent, reg, shift) \
    - imx_clk_hw_gate3(name, parent, reg, shift)->clk
    + to_clk(imx_clk_hw_gate3(name, parent, reg, shift))

    #define imx_clk_gate4(name, parent, reg, shift) \
    - imx_clk_hw_gate4(name, parent, reg, shift)->clk
    + to_clk(imx_clk_hw_gate4(name, parent, reg, shift))

    #define imx_clk_mux(name, reg, shift, width, parents, num_parents) \
    - imx_clk_hw_mux(name, reg, shift, width, parents, num_parents)->clk
    + to_clk(imx_clk_hw_mux(name, reg, shift, width, parents, num_parents))

    struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
    void __iomem *base, const struct imx_pll14xx_clk *pll_clk);
    @@ -195,6 +195,13 @@ struct clk_hw *imx_clk_hw_fixup_mux(const char *name, void __iomem *reg,
    u8 shift, u8 width, const char * const *parents,
    int num_parents, void (*fixup)(u32 *val));

    +static inline struct clk *to_clk(struct clk_hw *hw)
    +{
    + if (IS_ERR_OR_NULL(hw))
    + return ERR_CAST(hw);
    + return hw->clk;
    +}
    +
    static inline struct clk *imx_clk_fixed(const char *name, int rate)
    {
    return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
    --
    2.20.1
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