Messages in this thread | | | Date | Thu, 13 Feb 2020 11:15:38 +0100 | From | Peter Zijlstra <> | Subject | Re: [PATCH 7/7] microblaze: Do atomic operations by using exclusive ops |
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On Thu, Feb 13, 2020 at 10:04:03AM +0000, Will Deacon wrote: > On Thu, Feb 13, 2020 at 10:16:51AM +0100, Peter Zijlstra wrote: > > On Thu, Feb 13, 2020 at 09:58:49AM +0100, Peter Zijlstra wrote: > > > > > The thing is, your bog standard LL/SC _SHOULD_ fail the SC if someone > > > else does a regular store to the same variable. See the example in > > > Documentation/atomic_t.txt. > > > > > > That is, a competing SW/SWI should result in the interconnect responding > > > with something other than EXOKAY, the SWX should fail and MSR[C] <- 1. > > > > The thing is; we have code that relies on this behaviour. There are a > > few crusty SMP archs that sorta-kinda limp along (mostly by disabling > > some of the code and praying the rest doesn't trigger too often), but we > > really should not allow more broken SMP archs. > > I did find this in the linked pdf: > > | If the store [swx] is successful, the sequence of instructions from > | the semaphore load to the semaphore store appear to be executed > | atomically - no other device modified the semaphore location between > | the read and the update. > > which sounds like we're ok, although it could be better worded. > > One part I haven't figured out is what happens if you take an interrupt > between the lwx and the swx and whether you can end up succeeding thanks > to somebody else's reservation. Also, the manual is silent about the > interaction with TLB invalidation and just refers to "address" when > talking about the reservation. What happens if a user thread triggers > CoW while another is in the middle of a lwx/swx?
Page 79, Table 2-40 has the note:
"All of these events will clear the reservation bit, used together with the LWX and SWX instructions to implement mutual exclusion,..."
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