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    Subject[PATCH 4.9 106/116] ARM: dts: at91: sama5d3: fix maximum peripheral clock rates
    Date
    From: Alexandre Belloni <alexandre.belloni@bootlin.com>

    commit ee0aa926ddb0bd8ba59e33e3803b3b5804e3f5da upstream.

    Currently the maximum rate for peripheral clock is calculated based on a
    typical 133MHz MCK. The maximum frequency is defined in the datasheet as a
    ratio to MCK. Some sama5d3 platforms are using a 166MHz MCK. Update the
    device trees to match the maximum rate based on 166MHz.

    Reported-by: Karl Rudbæk Olsen <karl@micro-technic.com>
    Fixes: d2e8190b7916 ("ARM: at91/dt: define sama5d3 clocks")
    Link: https://lore.kernel.org/r/20200110172007.1253659-1-alexandre.belloni@bootlin.com
    Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    arch/arm/boot/dts/sama5d3.dtsi | 28 ++++++++++++++--------------
    arch/arm/boot/dts/sama5d3_can.dtsi | 4 ++--
    arch/arm/boot/dts/sama5d3_uart.dtsi | 4 ++--
    3 files changed, 18 insertions(+), 18 deletions(-)

    --- a/arch/arm/boot/dts/sama5d3.dtsi
    +++ b/arch/arm/boot/dts/sama5d3.dtsi
    @@ -1109,49 +1109,49 @@
    usart0_clk: usart0_clk {
    #clock-cells = <0>;
    reg = <12>;
    - atmel,clk-output-range = <0 66000000>;
    + atmel,clk-output-range = <0 83000000>;
    };

    usart1_clk: usart1_clk {
    #clock-cells = <0>;
    reg = <13>;
    - atmel,clk-output-range = <0 66000000>;
    + atmel,clk-output-range = <0 83000000>;
    };

    usart2_clk: usart2_clk {
    #clock-cells = <0>;
    reg = <14>;
    - atmel,clk-output-range = <0 66000000>;
    + atmel,clk-output-range = <0 83000000>;
    };

    usart3_clk: usart3_clk {
    #clock-cells = <0>;
    reg = <15>;
    - atmel,clk-output-range = <0 66000000>;
    + atmel,clk-output-range = <0 83000000>;
    };

    uart0_clk: uart0_clk {
    #clock-cells = <0>;
    reg = <16>;
    - atmel,clk-output-range = <0 66000000>;
    + atmel,clk-output-range = <0 83000000>;
    };

    twi0_clk: twi0_clk {
    reg = <18>;
    #clock-cells = <0>;
    - atmel,clk-output-range = <0 16625000>;
    + atmel,clk-output-range = <0 41500000>;
    };

    twi1_clk: twi1_clk {
    #clock-cells = <0>;
    reg = <19>;
    - atmel,clk-output-range = <0 16625000>;
    + atmel,clk-output-range = <0 41500000>;
    };

    twi2_clk: twi2_clk {
    #clock-cells = <0>;
    reg = <20>;
    - atmel,clk-output-range = <0 16625000>;
    + atmel,clk-output-range = <0 41500000>;
    };

    mci0_clk: mci0_clk {
    @@ -1167,19 +1167,19 @@
    spi0_clk: spi0_clk {
    #clock-cells = <0>;
    reg = <24>;
    - atmel,clk-output-range = <0 133000000>;
    + atmel,clk-output-range = <0 166000000>;
    };

    spi1_clk: spi1_clk {
    #clock-cells = <0>;
    reg = <25>;
    - atmel,clk-output-range = <0 133000000>;
    + atmel,clk-output-range = <0 166000000>;
    };

    tcb0_clk: tcb0_clk {
    #clock-cells = <0>;
    reg = <26>;
    - atmel,clk-output-range = <0 133000000>;
    + atmel,clk-output-range = <0 166000000>;
    };

    pwm_clk: pwm_clk {
    @@ -1190,7 +1190,7 @@
    adc_clk: adc_clk {
    #clock-cells = <0>;
    reg = <29>;
    - atmel,clk-output-range = <0 66000000>;
    + atmel,clk-output-range = <0 83000000>;
    };

    dma0_clk: dma0_clk {
    @@ -1221,13 +1221,13 @@
    ssc0_clk: ssc0_clk {
    #clock-cells = <0>;
    reg = <38>;
    - atmel,clk-output-range = <0 66000000>;
    + atmel,clk-output-range = <0 83000000>;
    };

    ssc1_clk: ssc1_clk {
    #clock-cells = <0>;
    reg = <39>;
    - atmel,clk-output-range = <0 66000000>;
    + atmel,clk-output-range = <0 83000000>;
    };

    sha_clk: sha_clk {
    --- a/arch/arm/boot/dts/sama5d3_can.dtsi
    +++ b/arch/arm/boot/dts/sama5d3_can.dtsi
    @@ -37,13 +37,13 @@
    can0_clk: can0_clk {
    #clock-cells = <0>;
    reg = <40>;
    - atmel,clk-output-range = <0 66000000>;
    + atmel,clk-output-range = <0 83000000>;
    };

    can1_clk: can1_clk {
    #clock-cells = <0>;
    reg = <41>;
    - atmel,clk-output-range = <0 66000000>;
    + atmel,clk-output-range = <0 83000000>;
    };
    };
    };
    --- a/arch/arm/boot/dts/sama5d3_uart.dtsi
    +++ b/arch/arm/boot/dts/sama5d3_uart.dtsi
    @@ -42,13 +42,13 @@
    uart0_clk: uart0_clk {
    #clock-cells = <0>;
    reg = <16>;
    - atmel,clk-output-range = <0 66000000>;
    + atmel,clk-output-range = <0 83000000>;
    };

    uart1_clk: uart1_clk {
    #clock-cells = <0>;
    reg = <17>;
    - atmel,clk-output-range = <0 66000000>;
    + atmel,clk-output-range = <0 83000000>;
    };
    };
    };

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