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SubjectRe: [PATCH v11 07/10] soc: mediatek: Add extra sram control
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On Tue, 2020-02-11 at 18:04 +0100, Matthias Brugger wrote:
>
> On 20/12/2019 04:46, Weiyi Lu wrote:
> > For some power domains like vpu_core on MT8183 whose sram need to
> > do clock and internal isolation while power on/off sram.
> > We add a flag "sram_iso_ctrl" in scp_domain_data to judge if we
> > need to do the extra sram isolation control or not.
> >
> > Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> > Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
> > ---
> > drivers/soc/mediatek/mtk-scpsys.c | 24 ++++++++++++++++++++++--
> > 1 file changed, 22 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
> > index 32be4b3..1972726 100644
> > --- a/drivers/soc/mediatek/mtk-scpsys.c
> > +++ b/drivers/soc/mediatek/mtk-scpsys.c
> > @@ -56,6 +56,8 @@
> > #define PWR_ON_BIT BIT(2)
> > #define PWR_ON_2ND_BIT BIT(3)
> > #define PWR_CLK_DIS_BIT BIT(4)
> > +#define PWR_SRAM_CLKISO_BIT BIT(5)
> > +#define PWR_SRAM_ISOINT_B_BIT BIT(6)
> >
> > #define PWR_STATUS_CONN BIT(1)
> > #define PWR_STATUS_DISP BIT(3)
> > @@ -86,6 +88,8 @@
> > * @name: The domain name.
> > * @sta_mask: The mask for power on/off status bit.
> > * @ctl_offs: The offset for main power control register.
> > + * @sram_iso_ctrl: The flag to judge if the power domain need to do
> > + * the extra sram isolation control.
> > * @sram_pdn_bits: The mask for sram power control bits.
> > * @sram_pdn_ack_bits: The mask for sram power control acked bits.
> > * @basic_clk_name: The basic clocks required by this power domain.
> > @@ -98,6 +102,7 @@ struct scp_domain_data {
> > const char *name;
> > u32 sta_mask;
> > int ctl_offs;
> > + bool sram_iso_ctrl;
>
> Why don't we put that into the caps variable? We have plenty of space left there
> and if needed we can bump up its value from u8 to u32.
>

Thanks for reminding, I'll put into caps in next version.

> > u32 sram_pdn_bits;
> > u32 sram_pdn_ack_bits;
> > const char *basic_clk_name[MAX_CLKS];
> > @@ -233,6 +238,14 @@ static int scpsys_sram_enable(struct scp_domain *scpd, void __iomem *ctl_addr)
> > return ret;
> > }
> >
> > + if (scpd->data->sram_iso_ctrl) {
> > + val = readl(ctl_addr) | PWR_SRAM_ISOINT_B_BIT;
> > + writel(val, ctl_addr);
> > + udelay(1);
> > + val &= ~PWR_SRAM_CLKISO_BIT;
> > + writel(val, ctl_addr);
> > + }
> > +
> > return 0;
> > }
> >
> > @@ -242,8 +255,15 @@ static int scpsys_sram_disable(struct scp_domain *scpd, void __iomem *ctl_addr)
> > u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
> > int tmp;
> >
> > - val = readl(ctl_addr);
> > - val |= scpd->data->sram_pdn_bits;
> > + if (scpd->data->sram_iso_ctrl) {
> > + val = readl(ctl_addr) | PWR_SRAM_CLKISO_BIT;
> > + writel(val, ctl_addr);
> > + val &= ~PWR_SRAM_ISOINT_B_BIT;
> > + writel(val, ctl_addr);
> > + udelay(1);
>
> Why do we need to wait here?
>

It's the restriction of sram isolation for both enable and disable stage
and we've confirmed 1us is safe.

> > + }
> > +
> > + val = readl(ctl_addr) | scpd->data->sram_pdn_bits;
> > writel(val, ctl_addr);
> >
> > /* Either wait until SRAM_PDN_ACK all 1 or 0 */
> >
>
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> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

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