Messages in this thread Patch in this message | | | From | Chris Packham <> | Subject | Re: [PATCH] MIPS: cavium_octeon: Fix syncw generation. | Date | Tue, 11 Feb 2020 21:37:59 +0000 |
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On Wed, 2020-02-12 at 10:24 +1300, Mark Tomlinson wrote: > The Cavium Octeon CPU uses a special sync instruction for implementing > wmb, and due to a CPU bug, the instruction must appear twice. A macro > had been defined to hide this: > > #define __SYNC_rpt(type) (1 + (type == __SYNC_wmb)) > > which was intended to evaluate to 2 for __SYNC_wmb, and 1 for any other > type of sync. However, this expression is evaluated by the assembler, > and not the compiler, and the result of '==' in the assembler is 0 or > -1, not 0 or 1 as it is in C. The net result was wmb() producing no code > at all. The simple fix in this patch is to change the '+' to '-'. > > Fixes: bf92927251b3 ("MIPS: barrier: Add __SYNC() infrastructure") > Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
For what it's worth
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> --- > arch/mips/include/asm/sync.h | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/arch/mips/include/asm/sync.h b/arch/mips/include/asm/sync.h > index 7c6a1095f5..aabd097933 100644 > --- a/arch/mips/include/asm/sync.h > +++ b/arch/mips/include/asm/sync.h > @@ -155,9 +155,11 @@ > * effective barrier as noted by commit 6b07d38aaa52 ("MIPS: Octeon: Use > * optimized memory barrier primitives."). Here we specify that the affected > * sync instructions should be emitted twice. > + * Note that this expression is evaluated by the assembler (not the compiler), > + * and that the assembler evaluates '==' as 0 or -1, not 0 or 1. > */ > #ifdef CONFIG_CPU_CAVIUM_OCTEON > -# define __SYNC_rpt(type) (1 + (type == __SYNC_wmb)) > +# define __SYNC_rpt(type) (1 - (type == __SYNC_wmb)) > #else > # define __SYNC_rpt(type) 1 > #endif
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