Messages in this thread | | | From | Martin Blumenstingl <> | Date | Sat, 5 Dec 2020 14:14:51 +0100 | Subject | Re: [PATCH v2 5/5] arm64: dts: meson: g12b: w400: fix PHY deassert timing requirements |
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On Tue, Dec 1, 2020 at 2:21 PM Stefan Agner <stefan@agner.ch> wrote: > > According to the datasheet (Rev. 1.9) the RTL8211F requires at least > 72ms "for internal circuits settling time" before accessing the PHY > egisters. On similar boards with the same PHY this fixes an issue where > Ethernet link would not come up when using ip link set down/up. > > Fixes: 2cd2310fca4c ("arm64: dts: meson-g12b-ugoos-am6: add initial device-tree") > Signed-off-by: Stefan Agner <stefan@agner.ch> with the "registers" typo above fixed: Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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