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    Subject[PATCH 3/3] powerpc/cacheinfo: Print correct cache-sibling map/list for L2 cache
    Date
    From: "Gautham R. Shenoy" <ego@linux.vnet.ibm.com>

    On POWER platforms where only some groups of threads within a core
    share the L2-cache (indicated by the ibm,thread-groups device-tree
    property), we currently print the incorrect shared_cpu_map/list for
    L2-cache in the sysfs.

    This patch reports the correct shared_cpu_map/list on such platforms.

    Example:
    On a platform with "ibm,thread-groups" set to
    00000001 00000002 00000004 00000000
    00000002 00000004 00000006 00000001
    00000003 00000005 00000007 00000002
    00000002 00000004 00000000 00000002
    00000004 00000006 00000001 00000003
    00000005 00000007

    This indicates that threads {0,2,4,6} in the core share the L2-cache
    and threads {1,3,5,7} in the core share the L2 cache.

    However, without the patch, the shared_cpu_map/list for L2 for CPUs 0,
    1 is reported in the sysfs as follows:

    /sys/devices/system/cpu/cpu0/cache/index2/shared_cpu_list:0-7
    /sys/devices/system/cpu/cpu0/cache/index2/shared_cpu_map:000000,000000ff

    /sys/devices/system/cpu/cpu1/cache/index2/shared_cpu_list:0-7
    /sys/devices/system/cpu/cpu1/cache/index2/shared_cpu_map:000000,000000ff

    With the patch, the shared_cpu_map/list for L2 cache for CPUs 0, 1 is
    correctly reported as follows:

    /sys/devices/system/cpu/cpu0/cache/index2/shared_cpu_list:0,2,4,6
    /sys/devices/system/cpu/cpu0/cache/index2/shared_cpu_map:000000,00000055

    /sys/devices/system/cpu/cpu1/cache/index2/shared_cpu_list:1,3,5,7
    /sys/devices/system/cpu/cpu1/cache/index2/shared_cpu_map:000000,000000aa

    Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
    ---
    arch/powerpc/kernel/cacheinfo.c | 7 +++++++
    1 file changed, 7 insertions(+)

    diff --git a/arch/powerpc/kernel/cacheinfo.c b/arch/powerpc/kernel/cacheinfo.c
    index 65ab9fc..1cc8f37 100644
    --- a/arch/powerpc/kernel/cacheinfo.c
    +++ b/arch/powerpc/kernel/cacheinfo.c
    @@ -651,15 +651,22 @@ static unsigned int index_dir_to_cpu(struct cache_index_dir *index)
    return dev->id;
    }

    +extern bool thread_group_shares_l2;
    /*
    * On big-core systems, each core has two groups of CPUs each of which
    * has its own L1-cache. The thread-siblings which share l1-cache with
    * @cpu can be obtained via cpu_smallcore_mask().
    + *
    + * On some big-core systems, the L2 cache is shared only between some
    + * groups of siblings. This is already parsed and encoded in
    + * cpu_l2_cache_mask().
    */
    static const struct cpumask *get_big_core_shared_cpu_map(int cpu, struct cache *cache)
    {
    if (cache->level == 1)
    return cpu_smallcore_mask(cpu);
    + if (cache->level == 2 && thread_group_shares_l2)
    + return cpu_l2_cache_mask(cpu);

    return &cache->shared_cpu_map;
    }
    --
    1.9.4
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