lkml.org 
[lkml]   [2020]   [Dec]   [28]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH 5.4 047/453] drm/amd/display: Init clock value by current vbios CLKs
    Date
    From: Brandon Syu <Brandon.Syu@amd.com>

    [ Upstream commit 7e0b367db85ef7b91399006253759a024eab7653 ]

    [Why]
    While booting into OS, driver updates DPP/DISP CLKs.
    But init clock value is zero which is invalid.

    [How]
    Get current clocks value to update init clocks.
    To avoid underflow.

    Signed-off-by: Brandon Syu <Brandon.Syu@amd.com>
    Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
    Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    .../drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 13 +++++++++++--
    1 file changed, 11 insertions(+), 2 deletions(-)

    diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
    index dd92f9c295b45..9f301f8575a54 100644
    --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
    +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
    @@ -97,8 +97,17 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base,
    new_clocks->dppclk_khz = 100000;
    }

    - if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
    - if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
    + /*
    + * Temporally ignore thew 0 cases for disp and dpp clks.
    + * We may have a new feature that requires 0 clks in the future.
    + */
    + if (new_clocks->dppclk_khz == 0 || new_clocks->dispclk_khz == 0) {
    + new_clocks->dppclk_khz = clk_mgr_base->clks.dppclk_khz;
    + new_clocks->dispclk_khz = clk_mgr_base->clks.dispclk_khz;
    + }
    +
    + if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) {
    + if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz)
    dpp_clock_lowered = true;
    clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
    update_dppclk = true;
    --
    2.27.0


    \
     
     \ /
      Last update: 2020-12-28 14:40    [W:6.384 / U:0.240 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site