lkml.org 
[lkml]   [2020]   [Dec]   [28]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH 4.19 027/346] PCI: qcom: Add missing reset for ipq806x
    Date
    From: Ansuel Smith <ansuelsmth@gmail.com>

    commit ee367e2cdd2202b5714982739e684543cd2cee0e upstream

    Add missing ext reset used by ipq8064 SoC in PCIe qcom driver.

    Link: https://lore.kernel.org/r/20200615210608.21469-5-ansuelsmth@gmail.com
    Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver")
    Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
    Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
    Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
    Reviewed-by: Rob Herring <robh@kernel.org>
    Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
    Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
    Cc: stable@vger.kernel.org # v4.5+
    [sudip: adjust context]
    Signed-off-by: Sudip Mukherjee <sudipm.mukherjee@gmail.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    drivers/pci/controller/dwc/pcie-qcom.c | 12 ++++++++++++
    1 file changed, 12 insertions(+)

    --- a/drivers/pci/controller/dwc/pcie-qcom.c
    +++ b/drivers/pci/controller/dwc/pcie-qcom.c
    @@ -108,6 +108,7 @@ struct qcom_pcie_resources_2_1_0 {
    struct reset_control *ahb_reset;
    struct reset_control *por_reset;
    struct reset_control *phy_reset;
    + struct reset_control *ext_reset;
    struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY];
    };

    @@ -269,6 +270,10 @@ static int qcom_pcie_get_resources_2_1_0
    if (IS_ERR(res->por_reset))
    return PTR_ERR(res->por_reset);

    + res->ext_reset = devm_reset_control_get_optional_exclusive(dev, "ext");
    + if (IS_ERR(res->ext_reset))
    + return PTR_ERR(res->ext_reset);
    +
    res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
    return PTR_ERR_OR_ZERO(res->phy_reset);
    }
    @@ -281,6 +286,7 @@ static void qcom_pcie_deinit_2_1_0(struc
    reset_control_assert(res->axi_reset);
    reset_control_assert(res->ahb_reset);
    reset_control_assert(res->por_reset);
    + reset_control_assert(res->ext_reset);
    reset_control_assert(res->pci_reset);
    clk_disable_unprepare(res->iface_clk);
    clk_disable_unprepare(res->core_clk);
    @@ -333,6 +339,12 @@ static int qcom_pcie_init_2_1_0(struct q
    goto err_deassert_ahb;
    }

    + ret = reset_control_deassert(res->ext_reset);
    + if (ret) {
    + dev_err(dev, "cannot deassert ext reset\n");
    + goto err_deassert_ahb;
    + }
    +
    /* enable PCIe clocks and resets */
    val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
    val &= ~BIT(0);

    \
     
     \ /
      Last update: 2020-12-28 14:24    [W:5.651 / U:0.120 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site