lkml.org 
[lkml]   [2020]   [Dec]   [23]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH v3 15/21] x86/fpu/xstate: Extend the table to map xstate components with features
    Date
    At compile-time xfeatures_mask_all includes all possible XCR0 features. At
    run-time fpu__init_system_xstate() clears features in xfeatures_mask_all
    that are not enabled in CPUID. It does this by looping through all possible
    XCR0 features.

    Update the code to handle the possibility that there will be gaps in the
    XCR0 feature bit numbers.

    No functional change, until hardware with bit number gaps in XCR0.

    Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com>
    Reviewed-by: Len Brown <len.brown@intel.com>
    Cc: x86@kernel.org
    Cc: linux-kernel@vger.kernel.org
    ---
    Changes from v1:
    * Rebased on the upstream kernel (5.10)
    ---
    arch/x86/kernel/fpu/xstate.c | 41 ++++++++++++++++++++++--------------
    1 file changed, 25 insertions(+), 16 deletions(-)

    diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c
    index 592e67ff6fa7..c2acfee581ba 100644
    --- a/arch/x86/kernel/fpu/xstate.c
    +++ b/arch/x86/kernel/fpu/xstate.c
    @@ -43,18 +43,23 @@ static const char *xfeature_names[] =
    "unknown xstate feature" ,
    };

    -static short xsave_cpuid_features[] __initdata = {
    - X86_FEATURE_FPU,
    - X86_FEATURE_XMM,
    - X86_FEATURE_AVX,
    - X86_FEATURE_MPX,
    - X86_FEATURE_MPX,
    - X86_FEATURE_AVX512F,
    - X86_FEATURE_AVX512F,
    - X86_FEATURE_AVX512F,
    - X86_FEATURE_INTEL_PT,
    - X86_FEATURE_PKU,
    - X86_FEATURE_ENQCMD,
    +struct xfeature_capflag_info {
    + int xfeature_idx;
    + short cpu_cap;
    +};
    +
    +static struct xfeature_capflag_info xfeature_capflags[] __initdata = {
    + { XFEATURE_FP, X86_FEATURE_FPU },
    + { XFEATURE_SSE, X86_FEATURE_XMM },
    + { XFEATURE_YMM, X86_FEATURE_AVX },
    + { XFEATURE_BNDREGS, X86_FEATURE_MPX },
    + { XFEATURE_BNDCSR, X86_FEATURE_MPX },
    + { XFEATURE_OPMASK, X86_FEATURE_AVX512F },
    + { XFEATURE_ZMM_Hi256, X86_FEATURE_AVX512F },
    + { XFEATURE_Hi16_ZMM, X86_FEATURE_AVX512F },
    + { XFEATURE_PT_UNIMPLEMENTED_SO_FAR, X86_FEATURE_INTEL_PT },
    + { XFEATURE_PKRU, X86_FEATURE_PKU },
    + { XFEATURE_PASID, X86_FEATURE_ENQCMD },
    };

    /*
    @@ -956,11 +961,15 @@ void __init fpu__init_system_xstate(void)
    }

    /*
    - * Clear XSAVE features that are disabled in the normal CPUID.
    + * Cross-check XSAVE feature with CPU capability flag. Clear the
    + * mask bit for disabled features.
    */
    - for (i = 0; i < ARRAY_SIZE(xsave_cpuid_features); i++) {
    - if (!boot_cpu_has(xsave_cpuid_features[i]))
    - xfeatures_mask_all &= ~BIT_ULL(i);
    + for (i = 0; i < ARRAY_SIZE(xfeature_capflags); i++) {
    + short cpu_cap = xfeature_capflags[i].cpu_cap;
    + int idx = xfeature_capflags[i].xfeature_idx;
    +
    + if (!boot_cpu_has(cpu_cap))
    + xfeatures_mask_all &= ~BIT_ULL(idx);
    }

    xfeatures_mask_all &= fpu__get_supported_xfeatures_mask();
    --
    2.17.1
    \
     
     \ /
      Last update: 2020-12-23 17:10    [W:2.314 / U:0.596 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site