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SubjectRe: [PATCH v7 3/4] phy: Add Sparx5 ethernet serdes PHY driver
Hi Steen,

I love your patch! Perhaps something to improve:

[auto build test WARNING on robh/for-next]
[also build test WARNING on linux/master linus/master v5.10-rc6 next-20201201]
[cannot apply to phy/next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url: https://github.com/0day-ci/linux/commits/Steen-Hegelund/Adding-the-Sparx5-Serdes-driver/20201202-211116
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: riscv-randconfig-r016-20201202 (attached as .config)
compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project 2671fccf0381769276ca8246ec0499adcb9b0355)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install riscv cross compiling tool for clang build
# apt-get install binutils-riscv64-linux-gnu
# https://github.com/0day-ci/linux/commit/f9670130c2b0d7ccd38a459e66d8da36b8edb7e0
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Steen-Hegelund/Adding-the-Sparx5-Serdes-driver/20201202-211116
git checkout f9670130c2b0d7ccd38a459e66d8da36b8edb7e0
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=riscv

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> drivers/phy/microchip/sparx5_serdes.c:2393:54: warning: variable 'idx' is uninitialized when used here [-Wuninitialized]
iores = platform_get_resource(pdev, IORESOURCE_MEM, idx);
^~~
drivers/phy/microchip/sparx5_serdes.c:2367:9: note: initialize the variable 'idx' to silence this warning
int idx;
^
= 0
1 warning generated.

vim +/idx +2393 drivers/phy/microchip/sparx5_serdes.c

2357
2358 static int sparx5_serdes_probe(struct platform_device *pdev)
2359 {
2360 struct device_node *np = pdev->dev.of_node;
2361 struct sparx5_serdes_private *priv;
2362 struct phy_provider *provider;
2363 struct resource *iores;
2364 void __iomem *iomem;
2365 unsigned long clock;
2366 struct clk *clk;
2367 int idx;
2368 int err;
2369
2370 if (!np && !pdev->dev.platform_data)
2371 return -ENODEV;
2372
2373 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
2374 if (!priv)
2375 return -ENOMEM;
2376
2377 platform_set_drvdata(pdev, priv);
2378 priv->dev = &pdev->dev;
2379
2380 /* Get coreclock */
2381 clk = devm_clk_get(priv->dev, NULL);
2382 if (IS_ERR(clk)) {
2383 dev_err(priv->dev, "Failed to get coreclock\n");
2384 return PTR_ERR(clk);
2385 }
2386 clock = clk_get_rate(clk);
2387 if (clock == 0) {
2388 dev_err(priv->dev, "Invalid coreclock %lu\n", clock);
2389 return -EINVAL;
2390 }
2391 priv->coreclock = clock;
2392
> 2393 iores = platform_get_resource(pdev, IORESOURCE_MEM, idx);
2394 iomem = devm_ioremap(priv->dev, iores->start, iores->end - iores->start + 1);
2395 if (IS_ERR(iomem)) {
2396 dev_err(priv->dev, "Unable to get serdes registers: %s\n",
2397 iores->name);
2398 return PTR_ERR(iomem);
2399 }
2400 for (idx = 0; idx < ARRAY_SIZE(sparx5_serdes_iomap); idx++) {
2401 struct sparx5_serdes_io_resource *iomap = &sparx5_serdes_iomap[idx];
2402
2403 priv->regs[iomap->id] = iomem + iomap->phys - iores->start;
2404 }
2405 for (idx = 0; idx < SPX5_SERDES_MAX; idx++) {
2406 err = sparx5_phy_create(priv, idx, &priv->phys[idx]);
2407 if (err)
2408 return err;
2409 }
2410
2411 provider = devm_of_phy_provider_register(priv->dev, sparx5_serdes_xlate);
2412
2413 return PTR_ERR_OR_ZERO(provider);
2414 }
2415

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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