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    Subject[PATCH v4 05/11] clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics
    Date
    From: Eugen Hristev <eugen.hristev@microchip.com>

    This SoC has the 5th divisor for the mck0 master clock.
    Adapt the characteristics accordingly.

    Reported-by: Mihai Sain <mihai.sain@microchip.com>
    Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
    Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
    ---
    drivers/clk/at91/sama7g5.c | 4 ++--
    1 file changed, 2 insertions(+), 2 deletions(-)

    diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
    index d3c3469d47d9..d685e22b2014 100644
    --- a/drivers/clk/at91/sama7g5.c
    +++ b/drivers/clk/at91/sama7g5.c
    @@ -775,13 +775,13 @@ static const struct clk_pll_characteristics pll_characteristics = {
    /* MCK0 characteristics. */
    static const struct clk_master_characteristics mck0_characteristics = {
    .output = { .min = 140000000, .max = 200000000 },
    - .divisors = { 1, 2, 4, 3 },
    + .divisors = { 1, 2, 4, 3, 5 },
    .have_div3_pres = 1,
    };

    /* MCK0 layout. */
    static const struct clk_master_layout mck0_layout = {
    - .mask = 0x373,
    + .mask = 0x773,
    .pres_shift = 4,
    .offset = 0x28,
    };
    --
    2.7.4
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